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SPRUHM8H–December 2013–Revised January 2019
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Copyright © 2013–2019, Texas Instruments Incorporated
Contents
3.6.3 PLLSLIP Detection .............................................................................................. 106
3.6.4 CPU1 and CPU2 PIE Vector Address Validity Check ...................................................... 106
3.6.5 NMIWDs .......................................................................................................... 107
3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 107
3.6.7 ECC Enabled Flash Memory................................................................................... 107
3.6.8 ERRORSTS Pin.................................................................................................. 107
3.7 Clocking ................................................................................................................... 108
3.7.1 Clock Sources.................................................................................................... 110
3.7.2 Derived Clocks ................................................................................................... 112
3.7.3 Device Clock Domains .......................................................................................... 112
3.7.4 XCLKOUT......................................................................................................... 113
3.7.5 Clock Connectivity ............................................................................................... 114
3.7.6 Clock Source and PLL Setup .................................................................................. 115
3.8 32-Bit CPU Timers 0/1/2................................................................................................. 118
3.9 Watchdog Timers ......................................................................................................... 120
3.9.1 Servicing the Watchdog Timer ................................................................................. 120
3.9.2 Minimum Window Check ....................................................................................... 121
3.9.3 Watchdog Reset or Watchdog Interrupt Mode............................................................... 121
3.9.4 Watchdog Operation in Low Power Modes .................................................................. 122
3.9.5 Emulation Considerations ...................................................................................... 122
3.10 Low Power Modes ........................................................................................................ 123
3.10.1 IDLE .............................................................................................................. 123
3.10.2 STANDBY ....................................................................................................... 123
3.10.3 HALT ............................................................................................................. 124
3.10.4 HIB................................................................................................................ 124
3.11 Memory Controller Module .............................................................................................. 126
3.11.1 Functional Description ......................................................................................... 126
3.12 Flash and OTP Memory ................................................................................................. 134
3.12.1 Features.......................................................................................................... 134
3.12.2 Flash Tools ...................................................................................................... 134
3.12.3 Default Flash Configuration ................................................................................... 135
3.12.4 Flash Bank, OTP and Pump .................................................................................. 135
3.12.5 Flash Module Controller (FMC) ............................................................................... 135
3.12.6 Flash and OTP Power-Down Modes and Wakeup......................................................... 136
3.12.7 Flash and OTP Performance.................................................................................. 138
3.12.8 Flash Read Interface ........................................................................................... 138
3.12.9 Erase/Program Flash........................................................................................... 140
3.12.10 Error Correction Code (ECC) Protection ................................................................... 141
3.12.11 Reserved Locations Within Flash and OTP ............................................................... 145
3.12.12 Procedure to Change the Flash Control Registers ....................................................... 145
3.12.13 Flash Pump Ownership Semaphore........................................................................ 145
3.13 Dual Code Security Module (DCSM)................................................................................... 147
3.13.1 Functional Description ......................................................................................... 147
3.13.2 CSM Impact on Other On-Chip Resources ................................................................. 153
3.13.3 Incorporating Code Security in User Applications.......................................................... 154
3.14 JTAG ....................................................................................................................... 158
3.15 F2837xD System Control Registers.................................................................................... 160
3.15.1 F2837xD System Control Base Addresses ................................................................. 160
3.15.2 CPUTIMER_REGS Registers................................................................................. 161
3.15.3 PIE_CTRL_REGS Registers .................................................................................. 168
3.15.4 WD_REGS Registers .......................................................................................... 220
3.15.5 NMI_INTRUPT_REGS Registers............................................................................. 226
3.15.6 XINT_REGS Registers......................................................................................... 240
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