QSFP-DD-CMIS-rev4p0.pdf_cmis-4.0

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Published Rev 4.0

Common Management Interface Specification Page 1

Common Management Interface Specification

Rev 4.0 May 8, 2019

Abstract: This document defines the Common Management Interface Specification (CMIS) that may be used by

pluggable modules with host to module management communication based on a Two-Wire-Interface (TWI), such

as QSFP Double Density (QSFP-DD), OSFP, COBO, QSFP, and SFP-DD. This document provides a common

specification for systems manufacturers, system integrators, and suppliers of modules and transceivers.

POINTS OF CONTACT:

Tom Palkert

Mark Nowell

Scott Sommers

Technical Editor

Co-Chair

Molex

Cisco

Molex

2222 Wellington Court

170 West Tasman Dr

2222 Wellington Court

Lisle, IL 60532-1682

San Jose, CA 95134

Lisle, IL 60532-1682

Ph: +1 (952)-200-8542

Ph: +1 (613)-254-3391

Ph: +1 (630)-527-4317

tom.palkert at molex.com

mnowell at cisco.com

scott.sommers at molex.com

Limitation on use of Information:

This specification is provided "AS IS" with NO WARRANTIES whatsoever and therefore the provision of this

specification does not include any warranty of merchantability, noninfringement, fitness for a particular purpose,

or any other warranty otherwise arising out of any proposal, specification or sample. The authors further disclaim

all liability, including liability for infringement of any proprietary rights, relating to use of information in this

specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is

granted herein.

Permissions:

You are authorized to download, reproduce and distribute this document. All other rights are reserved. The

provision of this document should not be construed as the granting of any right to practice, make, use or

otherwise develop products that are based on the document. Any and all IP rights related to this document and

the designs disclosed within, except for the rights expressly mentioned above, are reserved by the respective

owners of those IP rights.

Published Rev 4.0

Common Management Interface Specification Page 4

6.2.1

Functional Module Capabilities – Applications 33

6.2.1.1 Advertising Methodology 34

6.2.2 Logical Module Use – Data Paths 36

6.2.3 Data Path Configuration – Control Sets 36

6.2.3.1 Control Set Usage 37

6.2.3.2 Initialization Sequence Examples 38

6.2.4 Signal Integrity Controls 39

6.2.4.1 Tx Input Equalization Control 39

6.2.4.2 Rx Output Emphasis Control 40

6.2.4.3 Rx Output Amplitude Control 40

6.2.4.4 Tx Input Eq Adaptation Store/Recall Methodology 40

6.3 Module Behavioral Model 42

6.3.1 Module State Machine 42

6.3.1.1 Module State Machine, paged memory modules 42

6.3.1.2 Module State Machine, flat memory modules 47

6.3.1.3 Module Power Mode control 48

6.3.1.4 Resetting State 48

6.3.1.5 Reset State 49

6.3.1.6 MgmtInit State 49

6.3.1.7 ModuleLowPwr State 50

6.3.1.8 ModulePwrUp state 50

6.3.1.9 ModuleReady State 50

6.3.1.10 ModulePwrDn State 51

6.3.1.11 Fault State 51

6.3.2 Data Path State Machine 51

6.3.2.1 Data Path control and status 56

6.3.2.2 DataPathDeactivated State 57

6.3.2.3 DataPathInit State 57

6.3.2.4 DataPathInitialized State 58

6.3.2.5 DataPathDeinit State 58

6.3.2.6 DataPathTxTurnOn State 59

6.3.2.7 DataPathActivated State 60

6.3.2.8 DataPathTxTurnOff State 60

6.3.3 Interrupt Flag Conformance per State 61

6.3.3.1 Module Flag Conformance per State 61

6.3.3.2 Lane-Specific Flag Conformance per State 62

7 Advanced Management Features 64

7.1 Versatile Diagnostics Monitoring (VDM) 64

7.1.1 Overview 64

7.1.2 PAM4 Monitored Parameters 65

7.1.2.1 SNR 66

7.1.2.2 PAM Level Transition Parameter 66

7.1.2.3 Error Metrics 67

7.1.3 DWDM Monitored Parameters 68

7.1.3.1 TEC Current 68

7.1.3.2 Laser Frequency 68

7.1.3.3 Laser Temperature 68

7.2 Command Data Block (CDB) Message Communication 69

7.2.1 CDB support levels 69

7.2.1.1 Sequential CDB (foreground only) 70

7.2.1.2 One CDB with parallel register access (background mode) 70

7.2.1.3 Two CDB instances with parallel register access (background mode) 70

7.2.2 Firmware Upgrade Commands in CDB. 71

7.2.2.1 Firmware Upgrade using CDB 71

7.2.2.2 Firmware Readback using CDB 72

Published Rev 4.0

Common Management Interface Specification Page 5

7.2.3

Performance Monitoring using CDB. 74

7.3 Module Boot Record (MBR) 75

8 Module Management Memory Map 76

8.1 Overview 76

8.1.1 Memory Structure and Mapping 76

8.1.2 Supported Pages 76

8.1.3 General Specifications and Conventions 78

8.1.3.1 Referring to Bytes and Fields 78

8.1.3.2 Reserved Bytes, Fields, or Bits 78

8.1.3.3 Custom Bytes or Fields 78

8.1.3.4 Register Default Values 79

8.2 Lower Memory Page 00h (Control and Status Essentials) 80

8.2.1 ID and Status 81

8.2.2 Lane Flag Summary 82

8.2.3 Module-Level Flags 83

8.2.4 Module-Level Monitors 84

8.2.5 Module Global Controls 85

8.2.6 Module-Level Flag Masks 85

8.2.7 CDB Status 87

8.2.8 Module Active Firmware Version 88

8.2.9 Application Advertising 89

8.2.10 Password Entry and Change 91

8.2.11 Bank Select Byte 91

8.2.12 Page Select Byte 91

8.3 Upper Memory - Page 00h (Administrative Information) 92

8.3.1 Identifier 92

8.3.2 Vendor Name (Page 00h, Bytes 129-144, RO, required) 92

8.3.3 Vendor Organizationally Unique Identifier (Page 00h, Bytes 145-147, RO, required) 93

8.3.4 Vendor Part Number (Page 00h, Bytes 148-163, RO, required) 93

8.3.5 Vendor Revision Number (Page 00h, Bytes 164-165, RO, required) 93

8.3.6 Vendor Serial Number (Page 00h, Bytes 166-181, RO, required) 93

8.3.7 Date Code 93

8.3.8 CLEI Code 93

8.3.9 Module Power Characteristics 93

8.3.10 Cable Assembly Length 94

8.3.11 Media Connector Type 94

8.3.12 Copper Cable Attenuation 95

8.3.13 Cable Assembly Lane Information 95

8.3.14 Media Interface Technology (required) 97

8.3.15 Page 00h Checksum 97

8.3.16 Custom Info (non-volatile) 97

8.4 Page 01h (Advertising) 98

8.4.1 Module Inactive Firmware and Hardware Revisions 98

8.4.2 Supported Link Length 99

8.4.3 Wavelength (Page 01h, Bytes 138 - 139, RO, RQD) 100

8.4.4 Wavelength Tolerance (Page 01h, Bytes 140 - 141, RO, RQD) 100

8.4.5 Implemented Memory Pages and Durations Advertising 100

8.4.6 Module Characteristics Advertising 102

8.4.7 Implemented Controls Advertisement 103

8.4.8 Implemented Flags Advertisement 104

8.4.9 Implemented Monitors Advertisement 104

8.4.10 Implemented Signal Integrity Controls Advertisement 105

8.4.11 CDB Support Advertisement 106

8.4.12 Additional Durations Advertising 108

8.4.13 Media Lane Assignment Options Advertising 109

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