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i.MX RT1064 Processor Reference
Manual
Document Number: IMXRT1064RM
Rev. 1, 12/2019
i.MX RT1064 Processor Reference Manual, Rev. 1, 12/2019
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About this Document
1.1 Audience....................................................................................................................................................................... 21
1.2 Organization..................................................................................................................................................................21
1.3 Suggested Reading........................................................................................................................................................21
1.4 Conventions.................................................................................................................................................................. 22
1.5 Register Access.............................................................................................................................................................24
1.6 Acronyms and Abbreviations....................................................................................................................................... 26
Chapter 2
Introduction
2.1 Introduction...................................................................................................................................................................29
2.2 Features.........................................................................................................................................................................31
2.3 Target Applications.......................................................................................................................................................33
2.4 Endianness Support.......................................................................................................................................................33
Chapter 3
Memory Maps
3.1 Memory system overview.............................................................................................................................................35
3.2 Arm Platform Memory Map......................................................................................................................................... 35
Chapter 4
Interrupts, DMA Events, and XBAR Assignments
4.1 Chip-specific Interrupt information.............................................................................................................................. 43
4.2 Overview.......................................................................................................................................................................43
4.3 CM7 interrupts..............................................................................................................................................................43
4.4 DMA Mux.....................................................................................................................................................................52
4.5 PIT Channel Assignments For Periodic DMA Triggering........................................................................................... 60
4.6 XBAR Resource Assignments......................................................................................................................................61
Chapter 5
Direct Memory Access Multiplexer (DMAMUX)
i.MX RT1064 Processor Reference Manual, Rev. 1, 12/2019
NXP Semiconductors 3
Section number Title Page
5.1 Chip-specific DMAMUX information......................................................................................................................... 75
5.2 Introduction...................................................................................................................................................................75
5.3 External signal description............................................................................................................................................77
5.4 Functional description...................................................................................................................................................77
5.5 Initialization/application information........................................................................................................................... 82
5.6 Memory map/register definition................................................................................................................................... 85
Chapter 6
Enhanced Direct Memory Access (eDMA)
6.1 Chip-specific eDMA information.................................................................................................................................89
6.2 Introduction...................................................................................................................................................................89
6.3 Modes of operation....................................................................................................................................................... 93
6.4 Functional description...................................................................................................................................................93
6.5 Initialization/application information........................................................................................................................... 99
6.6 Memory map/register definition................................................................................................................................... 115
Chapter 7
System Security
7.1 Chapter overview..........................................................................................................................................................175
7.2 Feature summary...........................................................................................................................................................175
7.3 High-Assurance Boot (HAB)........................................................................................................................................177
7.4 Secure Non-Volatile Storage (SNVS) module............................................................................................................. 180
7.5 Data Co-Processor (DCP).............................................................................................................................................181
7.6 Standalone True Random Number Generator (TRNG)................................................................................................182
7.7 On-Chip OTP Controller (OCOTP_CTRL)..................................................................................................................182
7.8 Central Security Unit (CSU).........................................................................................................................................183
7.9 System JTAG Controller (SJC).................................................................................................................................... 183
7.10 Bus Encryption Engine (BEE)......................................................................................................................................184
Chapter 8
System Debug
8.1 Overview.......................................................................................................................................................................185
8.2 Chip and Arm Platform Debug Architecture................................................................................................................185
i.MX RT1064 Processor Reference Manual, Rev. 1, 12/2019
4 NXP Semiconductors
Section number Title Page
8.3 Miscellaneous............................................................................................................................................................... 193
Chapter 9
System Boot
9.1 Chip-specific Boot Information.................................................................................................................................... 195
9.2 Overview.......................................................................................................................................................................197
9.3 Boot modes................................................................................................................................................................... 199
9.4 Device configuration.....................................................................................................................................................202
9.5 Device initialization......................................................................................................................................................205
9.6 Boot devices..................................................................................................................................................................210
9.7 Program image..............................................................................................................................................................241
9.8 Plugin image................................................................................................................................................................. 248
9.9 Serial Downloader........................................................................................................................................................ 248
9.10 Recovery devices.......................................................................................................................................................... 258
9.11 SD/MMC manufacture mode........................................................................................................................................259
9.12 High-Assurance Boot (HAB)........................................................................................................................................259
9.13 ROM APIs.................................................................................................................................................................... 261
Chapter 10
External Signals and Pin Multiplexing
10.1 Overview.......................................................................................................................................................................273
Chapter 11
IOMUX Controller (IOMUXC)
11.1 Overview.......................................................................................................................................................................303
11.2 Clocks........................................................................................................................................................................... 305
11.3 Functional description...................................................................................................................................................305
11.4 IOMUXC GPR Memory Map/Register Definition.......................................................................................................308
11.5 IOMUXC SNVS Memory Map/Register Definition.................................................................................................... 362
11.6 IOMUXC SNVS GPR Memory Map/Register Definition........................................................................................... 381
11.7 IOMUXC Memory Map/Register Definition............................................................................................................... 385
Chapter 12
General Purpose Input/Output (GPIO)
i.MX RT1064 Processor Reference Manual, Rev. 1, 12/2019
NXP Semiconductors 5
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