IEEEStd1149.1-2013.pdf_IEEE1149.1

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IEEE Standard for Test Access Port and

Boundary-Scan Architecture

Sponsored by the

Test Technology Standards Committee

IEEE

3 Park Avenue

New York, NY 10016-5997

USA

13 Ma

2013

IEEE Computer Society

IEEE Std 1149.1™-2013

(Revision of

IEEE Std 1149.1-2001)

Authorized licensed use limited to: University of Virginia Libraries. Downloaded on June 18,2014 at 05:29:00 UTC from IEEE Xplore. Restrictions apply.

Abstract: Circuitry that may be built into an integrated circuit to assist in the test, maintenance and

support of assembled printed circuit boards and the test of internal circuits is defined. The circuitry

includes a standard interface through which instructions and test data are communicated. A set of test

features is defined, including a boundary-scan register, such that the component is able to respond to a

minimum set of instructions designed to assist with testing of assembled printed circuit boards. Also, a

language is defined that allows rigorous structural description of the component-specific aspects of such

testability features, and a second language is defined that allows rigorous procedural description of how

the testability features may be used.

Keywords: boundary scan, boundary-scan architecture, Boundary-Scan Description Language (BSDL),

boundary-scan register, circuit boards, circuitry, IEEE 1149.1

, integrated circuit, printed circuit boards,

Procedural Description Language (PDL), test, test access port (TAP), very high speed integrated circuit

(VHSIC), VHSIC Hardware Description Language (VHDL)

•

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PDF: ISBN 978-0-7381-8263-6 STD98160

Print: ISBN 978-0-7381-8264-3 STDPD98160

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