JEDEC Standard No. 21C, Release 29 DDR4 SDRAM UDIMM Design Specification
Page 4.20.26-2 Revision 1.22
Table of Contents
1 Product Description .......................................................................................................... 5
2 Environmental Requirements........................................................................................... 6
3 Connector Pinout and Signal Description....................................................................... 7
4 Power Details ................................................................................................................... 12
4.1 DIMM Voltage Requirements ................................................................................................................12
4.2 Rules for Power-Up Sequence..............................................................................................................12
4.3 Feed Through Voltage (VFT).................................................................................................................13
4.4 12 V Power..............................................................................................................................................13
5 Component Details.......................................................................................................... 14
5.1 Component Types and Placement .......................................................................................................17
5.2 Decoupling Guidelines..........................................................................................................................17
6 DIMM Design Details ....................................................................................................... 18
6.1 Signal Groups ........................................................................................................................................18
6.2 Explanation of Net Structure Diagrams...............................................................................................18
6.3 General Net Structure Routing Rules ..................................................................................................19
6.3.1 Clock, Control, and Address/Command Groups ........................................................... 19
6.3.2 Lead-in vs. Loaded Sections ......................................................................................... 20
6.3.3 Length/Delay Matching to SDRAM Devices ..................................................................20
6.3.4 Velocity Compensation..................................................................................................21
6.3.5 Load/Delay Compensation ............................................................................................21
6.3.6 Data and Strobe Group .................................................................................................21
6.3.7 ALERT_n Wiring............................................................................................................22
6.3.8 Via Compensation .........................................................................................................22
6.3.9 Plane Referencing .........................................................................................................23
6.4 Rules for Higher Speeds (2666 Mb/s or Higher...................................................................................24
6.5 Address Mirroring..................................................................................................................................24
6.6 DIMM Routing Space Constraints ........................................................................................................25
6.7 DIMM Physical Requirements...............................................................................................................26
6.7.1 Via Size ......................................................................................................................... 26
6.7.2 Component Pad Sizes and Geometry...........................................................................26
6.7.3 DRAM Package Size .....................................................................................................26
6.7.4 Clock Termination .........................................................................................................27
6.7.5 DQ Stub Resistor ..........................................................................................................27
6.7.6 ZQ Calibration Wiring ....................................................................................................27
6.7.7 TEN Wiring ....................................................................................................................27
6.8 Reference Stackups...............................................................................................................................28
6.9 Impedance Targets ................................................................................................................................30
6.10 SPD-TSE Wiring and Placement...........................................................................................................31
6.11 DQ Mapping to Support CRC................................................................................................................32
7 Serial Presence Detect.................................................................................................... 35
7.1 Serial Presence Detect Definition.........................................................................................................35
8 Product Label................................................................................................................... 37
8.1 DDR4 DIMM Label Format for DRAM-only module types...................................................................37
8.2 DDR4 DIMM Label Format for Hybrid module types...........................................................................42
9 JEDEC Process................................................................................................................ 49
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