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SOLUTIONS MANUAL
OPERATING SYSTEMS:
INTERNALS AND DESIGN PRINCIPLES
SIXTH EDITION
WILLIAM STALLINGS
Copyright 2008: William Stallings
-2-
© 2008 by William Stallings
All rights reserved. No part
of this document may be
reproduced, in any form or
by any means, or posted on
the Internet, without
permission in writing from
the author. Selected
solutions may be shared
with students, provided that
they are not available,
unsecured, on the Web.
-3-
NOTICE
This manual contains solutions to the review questions and
homework problems in Operating Systems, Sixth Edition. If you
spot an error in a solution or in the wording of a problem, I
would greatly appreciate it if you would forward the
information via email to ws@shore.net. An errata sheet for
this manual, if needed, is available at
http://www.box.net/public/ig0eifhfxu . File name is
S-OS6e-mmyy
W.S.
-4-
Chapter 1 Computer System Overview...............................................................5
Chapter 2 Operating System Overview.............................................................11
Chapter 3 Process Description and Control......................................................14
Chapter 4 Threads, SMP and Microkernels ......................................................19
Chapter 5 Concurrency: Mutual Exclusion and Synchronization.................24
Chapter 6 Concurrency: Deadlock and Starvation ..........................................37
Chapter 7 Memory Management .......................................................................46
Chapter 8 Virtual Memory ..................................................................................51
Chapter 9 Uniprocessor Scheduling...................................................................59
Chapter 10 Multiprocessor and Real-Time Scheduling ..................................72
Chapter 11 I/O Management and Disk Scheduling........................................77
Chapter 12 File Management ..............................................................................83
Chapter 13 Embedded Operating Systems .......................................................87
Chapter 14 Computer Security Threats .............................................................92
Chapter 15 Computer Security Techniques ......................................................94
Chapter 16 Distributed Processing, Client/Server, and Clusters................101
Chapter 17 Networking .....................................................................................104
Chapter 18 Distributed Process Management ................................................107
Appendix A Topics in Concurrency ................................................................110
TABLE OF CONTENTS
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CHAPTER 1 COMPUTER SYSTEM OVERVIEW
A
A
NSWERS TO
NSWERS TO
Q
Q
UESTIONS
UESTIONS
1.1 A main memory, which stores both data and instructions: an arithmetic and logic
unit (ALU) capable of operating on binary data; a control unit, which interprets the
instructions in memory and causes them to be executed; and input and output
(I/O) equipment operated by the control unit.
1.2 User-visible registers: Enable the machine- or assembly-language programmer to
minimize main memory references by optimizing register use. For high-level
languages, an optimizing compiler will attempt to make intelligent choices of which
variables to assign to registers and which to main memory locations. Some high-
level languages, such as C, allow the programmer to suggest to the compiler which
variables should be held in registers. Control and status registers: Used by the
processor to control the operation of the processor and by privileged, operating
system routines to control the execution of programs.
1.3 These actions fall into four categories: Processor-memory: Data may be transferred
from processor to memory or from memory to processor. Processor-I/O: Data may
be transferred to or from a peripheral device by transferring between the processor
and an I/O module. Data processing: The processor may perform some arithmetic
or logic operation on data. Control: An instruction may specify that the sequence of
execution be altered.
1.4 An interrupt is a mechanism by which other modules (I/O, memory) may interrupt
the normal sequencing of the processor.
1.5 Two approaches can be taken to dealing with multiple interrupts. The first is to
disable interrupts while an interrupt is being processed. A second approach is to
define priorities for interrupts and to allow an interrupt of higher priority to cause a
lower-priority interrupt handler to be interrupted.
1.6 The three key characteristics of memory are cost, capacity, and access time.
1.7 Cache memory is a memory that is smaller and faster than main memory and that
is interposed between the processor and main memory. The cache acts as a buffer
for recently used memory locations.
1.8 Programmed I/O: The processor issues an I/O command, on behalf of a process, to
an I/O module; that process then busy-waits for the operation to be completed
before proceeding. Interrupt-driven I/O: The processor issues an I/O command on
behalf of a process, continues to execute subsequent instructions, and is interrupted
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