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ES7210ConfidentialDS.pdf
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FEATURES • High performance multi-bit delta-sigma audio ADC • 102 dB signal to noise ratio • -85 dB THD+N • 24-bit, 8 to 200 kHz sampling frequency • I 2 S/PCM master or slave serial data port • Support TDM • 256/384Fs, USB 12/24 MHz and other non standard audio system clocks • Low power standby mode
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1
High Performance Four Channels Audio ADC
FEATURES
• High performance multi-bit delta-sigma
audio ADC
• 102 dB signal to noise ratio
• -85 dB THD+N
• 24-bit, 8 to 200 kHz sampling frequency
• I
2
S/PCM master or slave serial data port
• Support TDM
• 256/384Fs, USB 12/24 MHz and other
non standard audio system clocks
• Low power standby mode
APPLICATIONS
• Mic array
• Smart speaker
• Far field voice capture
ORDERING INFORMATION
ES7210 -40°C ~ +85°C
QFN-32
BLOCK DIAGRAM
ES7210
MIC1P/MIC1N
MIC2P/MIC2N
MIC3P/MIC3N
MIC4P/MIC4N
Multi-bit
Delta-sigma
Modulator
Audio
Data
Interface
DSP
Clock Manager
Sample Rate Detector
I
2
C
Interface
SDOUT1/TDMOUT
SCLK
LRCK
MCLK CCLK CDATA AD0 AD1
SDOUT2/TDMIN
Everest Semiconductor Confidential ES7210
Revision 2.0 2 February 2018
1. PIN OUT AND DESCRIPTION ................................................................................................ 4
2. TYPICAL APPLICATION CIRCUIT .......................................................................................... 5
3. CLOCK MODES AND SAMPLING FREQUENCIES ............................................................... 5
4. MICRO-CONTROLLER CONFIGURATION INTERFACE ...................................................... 5
5. DIGITAL AUDIO INTERFACE .................................................................................................. 7
6. ELECTRICAL CHARACTERISTICS ....................................................................................... 9
ABSOLUTE MAXIMUM RATINGS .................................................................................................. 9
RECOMMENDED OPERATING CONDITIONS ................................................................................ 9
ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS .......................................... 9
POWER CONSUMPTION CHARACTERISTICS .............................................................................. 10
SERIAL AUDIO PORT SWITCHING SPECIFICATIONS ................................................................... 10
I
2
C SWITCHING SPECIFICATIONS ............................................................................................... 11
7. CONFIGURATION REGISTER DEFINITION ........................................................................ 12
REGISTER 0X00 – RESET CONTROL, DEFAULT 00110010 .......................................................... 12
REGISTER 0X01 – CLOCK OFF, DEFAULT 00100000 ................................................................... 12
REGISTER 0X02 – MAIN CLOCK CONTROL, DEFAULT 00000010 ............................................... 12
REGISTER 0X03 – MASTER CLOCK CONTROL, DEFAULT 00000100 ........................................... 13
REGISTER 0X04 – MASTER LRCK DIVIDER 1, DEFAULT 00000001 ............................................. 13
REGISTER 0X05 – MASTER LRCK DIVIDER 0, DEFAULT 00000000 ............................................. 13
REGISTER 0X06 – POWER DOWN, DEFAULT 00000000 ............................................................ 13
REGISTER 0X07 – ADC OSR CONFIG, DEFAULT 00100000 ......................................................... 13
REGISTER 0X08 – MODE CONFIG, DEFAULT 00010000 ............................................................. 13
REGISTER 0X09 – TIME CONTROL 0 FOR CHIP INITIALIZATION, DEFAULT 01000000 ............... 14
REGISTER 0X0A – TIME CONTROL 1 FOR CHIP INITIALIZATION, DEFAULT 01000000 ............... 14
REGISTER 0X0B – CHIP STATUS, DEFAULT 00000000 ................................................................ 14
REGISTER 0X0C – INTERRUPT CONTROL, DEFAULT 00000000 .................................................. 14
REGISTER 0X0D – MISC. CONTROL, DEFAULT 00001001 .......................................................... 15
REGISTER 0X10 – DMIC CONTROL, DEFAULT 00000000 ........................................................... 15
REGISTER 0X11 – SDP INTERFACE CONFIG 1, DEFAULT 00000000 ........................................... 15
REGISTER 0X12 – SDP INTERFACE CONFIG 2, DEFAULT 00000000 ........................................... 16
REGISTER 0X13 – ADC AUTOMUTE CONTROL, DEFAULT 00000000 ......................................... 16
REGISTER 0X14 – ADC34 MUTE CONTROL, DEFAULT 00000000 ............................................... 16
REGISTER 0X15 – ADC12 MUTE CONTROL, DEFAULT 00000000 ............................................... 17
REGISTER 0X16 – ALC SELECT, DEFAULT 00000000 .................................................................. 17
REGISTER 0X17 – ALC COMMON CONFIG 1, DEFAULT 00000000 ............................................. 18
Everest Semiconductor Confidential ES7210
Revision 2.0 3 February 2018
REGISTER 0X18 – ADC34 ALC LEVEL, DEFAULT 11110111 ......................................................... 18
REGISTER 0X19 – ADC12 ALC LEVEL, DEFAULT 11110111 ........................................................ 19
REGISTER 0X1A – ALC COMMON CONFIG2, DEFAULT 00000000 ............................................. 20
REGISTER 0X1B – ADC4 MAX GAIN, DEFAULT 10111111 .......................................................... 20
REGISTER 0X1C – ADC3 MAX GAIN, DEFAULT 10111111 .......................................................... 20
REGISTER 0X1D – ADC2 MAX GAIN, DEFAULT 10111111 .......................................................... 20
REGISTER 0X1E – ADC1 MAX GAIN, DEFAULT 10111111 .......................................................... 21
REGISTER 0X20 – ADC34 HPF2, DEFAULT 00100110 ................................................................. 21
REGISTER 0X21 – ADC34 HPF1, DEFAULT 00100110 ................................................................. 21
REGISTER 0X22 – ADC12 HPF1, DEFAULT 00000110 ................................................................. 21
REGISTER 0X23 – ADC12 HPF2, DEFAULT 00100110 ................................................................. 21
REGISTER 0X24 TO 3X37 – EQ COEFFICIENTS AUTOMATICLLY GENERATED BY MATLAB ......... 22
REGISTER 0X3D – CHIP ID1, DEFAULT 01110010 ...................................................................... 22
REGISTER 0X3E – CHIP ID0, DEFAULT 00010000 ....................................................................... 22
REGISTER 0X3F – CHIP VERSION, DEFAULT 00000000 .............................................................. 22
REGISTER 0X40 – ANALOG SYSTEM, DEFAULT 10000000 ......................................................... 22
REGISTER 0X41 – MIC1/2 BIAS, DEFAULT 01110001 ................................................................. 22
REGISTER 0X42 – MIC3/4 BIAS, DEFAULT 01110001 ................................................................. 23
REGISTER 0X43 – MIC1 GAIN, DEFAULT 00000000 ................................................................... 23
REGISTER 0X44 – MIC2 GAIN, DEFAULT 00000000 ................................................................... 24
REGISTER 0X45 – MIC3 GAIN, DEFAULT 00000000 ................................................................... 24
REGISTER 0X46 – MIC4 GAIN, DEFAULT 00000000 ................................................................... 24
REGISTER 0X47 – MIC1 LOW POWER, DEFAULT 00000000 ...................................................... 25
REGISTER 0X48 – MIC2 LOW POWER, DEFAULT 00000000 ...................................................... 25
REGISTER 0X49 – MIC3 LOW POWER, DEFAULT 00000000 ...................................................... 25
REGISTER 0X4A – MIC4 LOW POWER, DEFAULT 00000000 ...................................................... 26
REGISTER 0X4B – MIC1/2 POWER DOWN, DEFAULT 11111111 ............................................... 26
REGISTER 0X4C – MIC3/4 POWER DOWN, DEFAULT 11111111 ............................................... 26
8. PACKAGE .............................................................................................................................. 28
9. CORPORATE INFORMATION .............................................................................................. 29
Everest Semiconductor Confidential ES7210
Revision 2.0 4 February 2018
1. PIN OUT AND DESCRIPTION
Pin Name Pin number Input or Output Pin Description
CCLK, CDATA 3, 4 I/O I
2
C clock and data
AD0, AD1 1, 2 I I
2
C address
MCLK
5
I
Master clock
SCLK
9
I/O
Serial data bit clock
LRCK
10
I/O
Serial data left and right channel frame clock
SDOUT1/TDMOUT
SDOUT2/TDMIN
11
12
O
I/O
Serial data output or TDM data input and output
INT
13
O
Interrupt
DMIC_CLK
14
I
Digital mic clock
MIC1P, MIC1N
MIC2P, MIC2N
MIC3P, MIC3N
MIC4P, MIC4N
16, 15
19, 20
31, 32
28, 27
Analog Mic input
MICBIAS12
MICBIAS34
24
26
Analog Mic bias
VDDP 6 Analog Power supply for the digital input and output
VDDD, GNDD 7, 8 Analog Digital power supply
VDDA, GNDA
22, 21
Analog
Analog power supply
VDDM
23
Analog
Analog power supply
REFP12, REFP34
17, 30
Analog
Filtering capacitor connection
REFQ12, REFQ34 18, 29 Analog Filtering capacitor connection
REFQM 25 Analog Filtering capacitor connection
ES7210
AD0
AD1
CDATA
CCLK
MCLK
VDDP
VDDD
GNDD
1
2
3
4
5
6
7
8
MIC1P
MIC1N
DMIC_CLK
INT
SDOUT2/TDMIN
SDOUT1/TDMOUT
LRCK
SCLK
16
15
14
13
12
11
10
9
MICBIAS12
VDDM
VDDA
GNDA
MIC2N
MIC2P
REFQ12
REFP12
24
23
22
21
20
19
18
17
REFQM
MICBIAS34
MIC4N
MIC4P
REFQ34
REFP34
MIC3P
MIC3N
25
26
27
28
29
30
31
32
Everest Semiconductor Confidential ES7210
Revision 2.0 5 February 2018
2. TYPICAL APPLICATION CIRCUIT
3. CLOCK MODES AND SAMPLING FREQUENCIES
The device supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz),
and some common non standard audio clocks (25 MHz, 26 MHz, etc).
According to the serial audio data sampling frequency (Fs), the device can work in two speed
modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges
from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.
The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.
4. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I
2
C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.
I
2
C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock
line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in
Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on
a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being
transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull
the CDATA low. The transfer rate of this interface can be up to 400 kbps.
AD0
1
AD1
2
CCLK
4
MCLK
5
VDDD
7
GNDD
8
CDATA
3
VDDP
6
SCL K
9
LRCK
10
SDOUT2/ TDMI N
12
I NT
13
MIC1N
15
MIC1P
16
SDOUT1/ TDMOUT
11
DMI C_CL K/ GPI O
14
REFP 12
17
REFQ12
18
MIC2N
20
GNDA
21
VDDM
23
MIC BI AS12
24
MIC2P
19
VDDA
22
REFQM
25
MIC BI AS34
26
MIC4P
28
REFQ34
29
MIC3P
31
MIC3N
32
MIC4N
27
REFP 34
30
ES7210
Everest
IIC
IIS
VDDC
VDDP
GPIO
100K
VDDP
100nF
100nF
For best performance,decoupling and filter capacitor should be located as close to the device package as possible
10uF 10uF 10uF 10uF 10uF
AGND
1R
10uF 100nF
VDDA
AGND
1R
10uF 100nF
VDDM
AGND
2.2uF
2.2uF
10nF
Mic4
AGND
2K
2.2uF
2.2uF
10nF 10nF 10nF
2K 2K 2K
AGND
AGND
Mic3
10uF
100nF
AGND
2.2uF
2.2uF
10nF
Mic2
AGND
2K
2.2uF
2.2uF
10nF 10nF 10nF
2K 2K 2K
AGND
AGND
Mic1
10uF
100nF
AGND
1uF
1uF
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