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CONFIDENTIAL FOR KAI YANG AT AVNET ASIA PTE LTD

1/15/2013 FB1PM

Data Sheet

BCM54640E

54640E-DS07-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 October 30, 2012

Quad Gigabit Ethernet Transceiver

GENERAL DESCRIPTION

FEATURES

The BCM54640E transceiver can support either four

SGMII-to-copper (10/100/1000BASE-T) interfaces or

four SGMII-to- Fiber (100BASE-FX, 1000BASE-X, or

SGMII-Slave) interfaces. When in SGMII-to-copper

mode, the PHY performs all of the physical layer

(PHY) functions for 1000BASE-T, 100BASE-TX, and

10BASE-T on standard Category 5 UTP cable. When in

SGMII-to-fiber mode, the PHY performs all of the

physical layer (PHY) functions for 100BASE-FX,

1000BASE-X, and SGMII-Slave. The BCM54640E is

designed to comply with the SGMII industry standard

and to exceed IEEE specifications for noise

cancellation and transmission jitter, providing

consistent and reliable operation over the broadest

range of existing cable plants.

The BCM54640E is based on the proven digital signal

processor technology of Broadcom, combining digital

adaptive equalizers, ADCs, phase-locked loops, line

drivers, encoders, decoders, echo cancelers,

crosstalk cancelers, and all other required support

circuitry integrated into a single monolithic CMOS

chip.

Designed for reliable operation over worst-case

Category 5 cable plants, the BCM54640E

automatically negotiates with any transceiver on the

opposite end of the wire to agree on an operating

speed. The PHY can also evaluate the condition of the

twisted-pair wiring to ensure that the wiring can

support operation at Gigabit speeds, and detect and

correct most common wiring problems. The device

continually monitors both the wiring and the

opposing transceiver and alerts the system if it

detects potential problems with reliable operation.

• Support for the following copper line interfaces:

–1000BASE-T

–100BASE-TX

–10BASE-T

• Support for the following Fiber line interfaces:

–100BASE-FX

–1000BASE-X

– SGMII-Slave

• Integrated twisted-pair termination resistors

• IEEE 802.3az compliant

– Supports Native EEE MACs

– Supports Legacy Non-EEE MACs using

AutogrEEEn® mode

• Synchronous Ethernet support

• IEEE Standard 1588-2008 (version 2)-compliant

• SGMII interface

•3.3V digital I/O

• Support for only two power supplies (1.2V and

3.3V)

• Line-side and switch-side loopback

• Ethernet@WireSpeed™

• Cable plant diagnostics that detects cable plant

impairments

•Programmable LEDs

• Robust Cable ESD (CESD) tolerance

• Low EMI emissions

• IEEE 1149.1 and 1149.6 (ACJTAG) boundary scan

• Package: 17 mm x 17 mm 256-pin FBGA

APPLICATIONS

• High-density Gigabit Ethernet (GbE) switches and

routers

CONFIDENTIAL FOR KAI YANG AT AVNET ASIA PTE LTD

1/15/2013 FB1PM

Revision HistoryBCM54640E Data Sheet

BROADCOM

October 30, 2012 • 54640E-DS07-R Page 3

BROADCOM CONFIDENTIAL

54640E-DS06-R 04/18/12 Added:

• “Expansion D 5Ch Counter Reset Register” on page 262and “Expansion

D 5Dh TX Time Stamp Information Register” on page 262.

Updated:

• Updated register bit field default values throughout document.

• “Multimode TX Digital-to-Analog Converter” on page 37: Changed

current driver output to voltage mode output.

• “IEEE-1588 Global Enable” on page 43: Updated procedure.

• “Enabling One-Step TC in the PHY” on page 43: Updated Example in

step 1.

• “GM Support” on page 43: Updated entire section.

• “SC Support” on page 44: Updated entire section: Updated procedure.

• “SYNC_IN Control” on page 45: Removed 2’b00 and 2’b01 from table.

• Table 9: “IEEE 1588 IPV6/UDP Packet Formats,” on page 49: Changed

Ethernet Type value.

• “Energy Efficient Ethernet” on page 50: Removed references to QSGMII

throughout section.

• Table 15: “Ball Descriptions,” on page 61: Corrected SAVDDR[3:1] bit

range in Power section.

• Figure 13: “SGMII Internal Loopback Mode (MDI RX/TX Suppressed),” on

page 91 through Figure 18: “Line-Side Loopback Mode with RX Data

Forwarded to Switch,” on page 96: Removed SLED_* and SL_* signals

from LED interface, removed bit range from MDIO and MDC signals,

removed TRD[3:0](8) through TRD[3:0](5) signals, and updated

SGOUT[4:1]±+/- and SGIN[4:1]± signals.

• Table 28: “Register Map,” on page 108:

– Added “1Ch: Auto-Detect Medium Register (Shadow Register

Selector 1Eh)” to 1000BASE-T/100BASE-TX/10BASE-T Registers.

– Added Expansion registers.

– Added Expansion D registers.

– Added Clause 45 registers.

– Added Top-Level MII registers.

• “1000BASE-T/100BASE-TX/10BASE-T PHY Identifier” on page 118:

Updated model number.

• “1Ch: Auto-Detect Medium Register” on page 193: Changed definition

for bits 7:5.

• “Expansion D Registers” on page 240: Added note regarding 1st PHY

port, PHYA[4:0]+0.

• “IEEE 1588 NSE NCO Register 1B (Offset 44h)” on page 256through “IEEE

1588 NSE NCO Register 3C (Offset 4Ah)” on page 257: Updated register

names.

• “IEEE 1588 Length Threshold Register (Offset 50h)” on page 259and

“IEEE 1588 Event Offset Register (Offset 51h)” on page 260: Updated bit

field descriptions.

Revision Date Change Description

CONFIDENTIAL FOR KAI YANG AT AVNET ASIA PTE LTD

1/15/2013 FB1PM

Revision HistoryBCM54640E Data Sheet

BROADCOM

October 30, 2012 • 54640E-DS07-R Page 4

BROADCOM CONFIDENTIAL

54640E-DS06-R

(continued)

• “Expansion D 53h TX Time Stamp Register LSBs” on page 260 through

“Expansion D 56h Heartbeat Register LSBs” on page 260: Updated

• “Expansion D 5Bh RX/TX 1588 Packet Counter Register” on page

261through “Expansion D 70h P1588 RX Port Link Delay MSB Register X

8” on page 264: Updated fields and descriptions.

• Table 222: “Twisted Pair Characteristics,” on page 281: Updated

parameter pins.

• Table 229: “Ordering Information,” on page 286: Added ambient

temperature data.

54640E-DS05-R 02/13/12 Updated:

• “1000BASE-X Registers 00h to 14h” on page 154

• “FIFO ELASTICITY[1]” on page 195

• “SGMII Register Descriptions Address 00h to 05h” on page 207

Added:

• “Expansion F3h: 1588 Timestamp/Heartbeat Read Start/End Register”

on page 243

Deleted:

• Unidirectional mode for 10/100/1000BASE-T

• Broadcom Serial Control Interface

• Expansion Register 0Bh: Port Interrupt Status (Port 1)

54640E-DS04-R 06/22/11 Updated:

• “Clean-up PLL Considerations” on page 53.

• “SGMII/SerDes Selector” on page 189.

• “1000BASE-X Auto-negotiation Parallel Detect Enable” on page 194

• Table 88: “Mode Control Register (Address 1Ch, Shadow 1Fh),” on

page 200

• “Mode Select Change” on page 227

• “Expansion Register 01h: Fiber Interrupt Status” and “Expansion

• Table 123: “Expansion Register 42h: Operating Mode Status,” on

page 240

• Table 130: “MDI/MAC Register Window Selector Register (Address

01h),” on page 245

• Table 189: “IEEE 1588 SYNOUT_TS_REG[15:0] (Address 4Ch),” Table

190: “IEEE 1588 SYNOUT_TS_REG[31:16] (Address 4Dh),” and Table 191:

“IEEE 1588 SYNOUT_TS_REG[47:32] (Address 4Eh),” on page 269

• Table 169: “Ordering Information,” on page 271

Revision Date Change Description

CONFIDENTIAL FOR KAI YANG AT AVNET ASIA PTE LTD

1/15/2013 FB1PM

Revision HistoryBCM54640E Data Sheet

BROADCOM

October 30, 2012 • 54640E-DS07-R Page 5

BROADCOM CONFIDENTIAL

54640E-DS03-R 05/20/11 Updated:

• Table 8: “Ball Descriptions,” on page 55.

• Table 81: “Shadow Register Selector (Address 14h – PHYA[4:0] + 0

Only),” on page 188

• “SGMII/SerDes Selector” on page 189

• “SGMII Register Descriptions Address 00h to 05h” on page 207

• Table 142: “IEEE 1588 Enable Control Register (Address 10h),” on page

253

• Table 144: “IEEE 1588 TX SOP/RX EVENT Message Mode Selection

• Table 145: “IEEE 1588 RX SOP Timestamp Enable Register (Address

13h),” on page 256

• Table 160: “IEEE 1588 Shadow Register Load (Offset 2Fh),” on page 261

• Table 187: “IEEE 1588 NSE NCO Register 3 (Address 4Ah),” on page 268

Added:

• Table 130: “MDI/MAC Register Window Selector Register (Address

01h),” on page 245

54640E-DS02-R 09/28/10 Updated:

• “IEEE-1588 Global Enable” on page 48

• “Native EEE Flow” on page 58

• “AutogrEEEn Mode” on page 60

• Figure 6: “Top View — Ball Location Diagram,” on page 74

• Figure 7: “Top View — Ball Name Location Diagram (Figure 1 of 2),” on

page 75

• Table 16: “Ballout Listed by Ball Name,” on page 77

• Table 17: “Ballout Listed by Ball Number,” on page 79

• “PHY Address” on page 86

• Table 71: “LED GPIO Control/Status Register (Address 1Ch, Shadow

Value 0Fh),” on page 175

• “Programmable LED Current Control” on page 175

• “SerDes 100BASE-FX Status Register” on page 178

• “Serdes 100BASE-FX Control Register” on page 180

• “Expansion D Registers” on page 232

• “REFCLK Input Timing (Single-Ended Mode)” on page 267

• “REFCLK Clock Input Timing (Differential Mode)” on page 268

• Table 225: “Ordering Information,” on page 280

54640E-DS01-R 04/12/10 Updated:

• “PHY Address” on page 80

Added:

• “Fiber Line-Side Loopback” on page 92

54640E-DS00-R 02/10/10 Initial release

Revision Date Change Description

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