5
潜在的瓶颈部位
Potential bottlenecks
芯片内高速缓存
视频存储器
系统内存
光栅化
CPU
顶点着色
(T&L)
三角形建立
片段着色
和光栅操作
纹理
帧缓冲
几何
命令
pre-TnL
cache
post-TnL cache
纹理高速
缓存
顶点变换
限制
像素着色
器限制
CPU 限
制
纹理带宽
限制
帧缓冲带宽限制
setup
限制
光栅限
制
AGP 传
输限制
The first real module that we encounter is the vertex Shader, also called the
vertex program units, and this is where you're going to do your transform and
lighting of vertices. These vertices then get put into some sort of vertex
cache that operates in different fashions. Some operate as FIFO’s, some, as
leased recently used, or LRU, and, obviously, current high-end cards have
larger caches than the older generation and mainstream cards. Then the
triangle setup stage is reached. This module reads vertices from the cache
and this is where basically the polygon is formed. Once the polygon is
formed, the rasterization is where it gets broken up into pixels. So now the
next stage only accepts pixels and this is the fragment shading or pixel
shader stage. The pixel shader stage is typically where a lot of time is spent
these days and we're going to spend a good amount of time analyzing this.
After the pixel shading stage is the raster operationm meaning the alpha
blend and stencil Z buffer. These can contribute to the bottleneck but
typically not. And, finally, you can have traffic from the pixel Shader and
raster module to the frame by frame back, right, and back because you can
do alpha blending, you need to read stenciling to read a Z and also the
fragment Shader can read textures so you can have a texture bottleneck as
you're accessing memory again.
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