library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD1602 is
##Port ( CLK : in std_logic;##--状态机时钟信号，同时也是液晶时钟信号，其周期应该满
足液晶数据的建立时间
##Reset:in std_logic;##
# ## ## #LCD_RS : out std_logic; --寄存器选择信号
# ## ## #LCD_RW : out std_logic; --液晶读写信号
# ## ## #LCD_EN : out std_logic; --液晶时钟信号
# ## ## #LED: out std_logic;
# ## ## #LCD_Data : out std_logic_vector(7 downto 0));##--液晶数据信号
end LCD1602;
architecture Behavioral of LCD1602 is
##type state is
(set_dlnf,set_cursor,set_dcb,set_cgram,write_cgram,set_ddram,write_LCD_Dat
a);
##signal Current_State:state;
##type ram1 is array(0 to 30) of std_logic_vector(7 downto 0);
##type ram2 is array(0 to 30) of std_logic_vector(7 downto 0);
##type ram3 is array(0 to 30) of std_logic_vector(7 downto 0);
constant
cgram1:ram1:=(x"46",x"50",x"47",x"41",x"2f",x"43",x"50",x"4c",x"44",x"20",
x"73",x"74",x"75",x"64",x"79",x"20",x"20",x"42",x"79",x"20",x"4d",x"49",x"4
1",x"4f",x"53",x"48",x"41",x"4e",x"4c",x"49",x"4e");
--显示我的名字的汉语拼音，以及 FPGA/CPLD study by MIAOSHANLIN
constant
cgram3:ram3:=(x"68",x"74",x"74",x"70",x"3a",x"2f",x"2f",x"6d",x"69",x"61",x
"6f",x"73",x"68",x"61",x"6e",x"6c",x"69",x"6e",x"2e",x"61",x"6e",x"79",x"32",
x"30",x"30",x"30",x"2e",x"63",x"6f",x"6d",x"2f");
--显示我的主页
constant
cgram2:ram2:=(x"51",x"51",x"3a",x"33",x"33",x"30",x"34",x"39",x"35",x"39",
x"30",x"38",x"20",x"20",x"20",x"20",x"54",x"65",x"6c",x"3a",x"31",x"33",x"39
",x"33",x"36",x"35",x"30",x"39",x"33",x"38",x"31");
--显示我的 QQ 号码和手机号码：QQ：330495908 Tel：13936509381
signal##CLK1# # : std_logic;
signal##Clk_Out : std_logic;
signal##LCD_Clk : std_logic;
signal##m# ## # :std_logic_vector(1 downto 0);
begin
##LCD_EN <=##Clk_Out ;
##LED <= Clk_Out;
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