Apollo3_Blue_MCU_Data_Sheet_v0_11_0.pdf_apollo3芯片

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Apollo3 Blue MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A3-0p11p0 Page 1 of 915 2020 Ambiq Micro, Inc.

Apollo3 Blue

MCU Datasheet

Doc. ID: DS-A3-0p11p0

Revision 0.11.0

April 2020

Apollo3 Blue MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A3-0p11p0 Page 2 of 915 2020 Ambiq Micro, Inc.

Ambiq Micro

Apollo3

MCU

Host

Processor

(optional)

SPI/I

Slave

Port

SPI/I

C Master,

UART

GPS / WiFi

Magnetometer

with Digital

Output

Gyroscope

with Digital

Output

Accelerometer

with Digital

Output

Typical Application Circuit for the Apollo3 MCU

External Flash

Multi-bit

SPI

Display

Features

Ultra-low supply current:

- 6 µA/MHz executing from FLASH or RAM at 3.3 V

- 1 µA deep sleep mode (BLE Off) with RTC at 3.3 V (BLE in

SD)

High-performance ARM Cortex-M4 Processor

- 48 MHz nominal clock frequency, with 96 MHz high perfor-

mance TurboSPOT™ Mode

- Floating point unit

- Memory protection unit

- Wake-up interrupt controller with 32 interrupts

Integrated Bluetooth

5 low-energy module

- RF sensitivity: -93 dBm (typical)

- TX: 3 mA @ 0 dBm, RX: 3 mA

- Tx peak output power: 4.0 dBm (max)

Ultra-low power memory:

- Up to 1 MB of flash memory for code/data

- Up to 384 KB of low leakage RAM for code/data

- 16 kB 2-way Associative/Direct-Mapped Cache

Ultra-low power interface for on- and off-chip sensors:

- 14 bit ADC at up to 1.2 MS/s, 15 selectable input channels

available

- Voltage Comparator

- Temperature sensor with +/- 3ºC accuracy after calibration

ISO7816 Secure interface

Flexible serial peripherals:

- 1x 2/4/8-bit SPI master interface (MSPI)

- 6x I

C/SPI masters for peripheral communication

- I

C/SPI slave for host communications

- 2x UART modules with 32-location Tx and Rx FIFOs

- PDM for mono and stereo audio microphone

- 1x I

S slave for PDM audio pass-through

Rich set of clock sources:

- 32.768 kHz XTAL oscillator

- Low frequency RC oscillator – 1.024 kHz

- High frequency RC oscillator – 48/96 MHz

- RTC based on Ambiq’s AM08X5/18X5 families

Wide operating range: 1.755-3.63 V, –40 to 85°C

Compact package:

1. The Bluetooth® word mark and logos are registered trademarks

owned by the Bluetooth SIG, Inc. and any use of such marks is under

license. Other trademarks and trade names are those of their respec-

tive owners.

- 3.37 x 3.25 mm(<0.35mm thk pkg) 66-pin CSP with 37 GPIO

- 5 x 5 mm (<0.5mm thk pkg) 81-pin BGA with 50 GPIO

Applications

Description

The Apollo MCU Family is an ultra-low power, highly integrated

microcontroller platform based on Ambiq Micro’s patented Sub-

threshold Power Optimized Technology (SPOT™) and designed

for battery-powered and portable, mobile devices. The Apollo3

Blue MCU sets a new standard in energy efficiency for battery-

powered devices with an integrated ARM Cortex-M4 processor

with Floating Point Unit and TurboSPOT™ increasing the compu-

tational capabilities of the ARM Cortex M4F core to 96MHz while

lowering the active power consumption to <6uA/MHz. This combi-

nation dramatically reduces energy consumption while still

enabling abundant application processing power to add greater

capability and extended life to battery operated devices.

The Apollo3 Blue brings several new features to Ambiq’s SPOT-

based Apollo MCU Family including an integrated DMA engine,

QSPI interface, and advanced stepper motor control for ultra-low

power analog watch hand management. With unprecedented

energy efficiency and PDM microphone inputs, the Apollo3 Blue

also forms the core of Ambiq’s Voice-on-SPOT™ reference

platform making it the perfect device for customers who want to

add always-on voice assistant integration and command

recognition to battery-powered devices. To increase design

flexibility and enable connections to the phone and cloud, the

Apollo3 Blue provides a dedicated second core for the ultra-low

power BLE5 connectivity platform providing superior RF

throughput and leaving plenty of resources available for user

applications.

▪ Voice-on-SPOT™ compatible for always-listening keyword

detect, audio command recognition and voice assistant integra-

tion in battery-powered devices including:

- Bluetooth headsets, earbuds, and truly wireless earbuds

- Remote and Gaming Controls

- Smart home

▪ Wearables including smart watches and fitness/activity trackers

▪ Hearing aids, Digital Health Monitoring and Sensing Devices

▪ Smart Home Automation, Security and Lighting control applica-

tions

Apollo3 Blue MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A3-0p11p0 Page 3 of 915 2020 Ambiq Micro, Inc.

Table of Content

1. Apollo3 Blue MCU Package Pins ..................................................................................... 47

1.1 Pin Configuration ....................................................................................................... 47

1.2 Pin Connections ......................................................................................................... 49

2. System Core ....................................................................................................................... 66

3. MCU Core Details ............................................................................................................. 68

3.1 Functional Overview .................................................................................................. 68

3.2 Interrupts .................................................................................................................... 69

3.3 Memory Map ............................................................................................................. 72

3.4 Memory Protection Unit (MPU) ................................................................................ 75

3.5 System Buses ............................................................................................................. 76

3.6 Power Management ................................................................................................... 77

3.6.1 Cortex-M4 Power Modes .................................................................................. 77

3.6.2 System Power Modes ........................................................................................ 78

3.6.3 Power Control ................................................................................................... 81

3.7 Debug Interfaces ........................................................................................................ 98

3.7.1 Debugger Attachment ....................................................................................... 98

3.7.2 Instrumentation Trace Macrocell (ITM) ........................................................... 98

3.7.3 Trace Port Interface Unit (TPIU) ...................................................................... 98

3.7.4 Faulting Address Trapping Hardware ............................................................... 98

3.8 ITM Registers ............................................................................................................ 99

3.8.1 Register Memory Map .................................................................................... 100

3.8.2 ITM Registers ................................................................................................. 102

3.9 MCUCTRL Registers .............................................................................................. 128

3.9.1 Register Memory Map .................................................................................... 129

3.9.2 MCUCTRL Registers ..................................................................................... 131

3.10 Memory Subsystem ............................................................................................... 161

3.10.1 Features ......................................................................................................... 161

3.10.2 Functional Overview ..................................................................................... 162

3.10.3 Flash Cache ................................................................................................... 163

3.10.4 SRAM Interface ............................................................................................ 178

4. Security ............................................................................................................................ 180

4.1 Functional Overview ................................................................................................ 180

4.2 Secure Boot .............................................................................................................. 180

4.3 Secure OTA ............................................................................................................. 180

4.4 Secure Key Storage .................................................................................................. 181

4.5 External Flash In-line Encrypt/Decrypt ................................................................... 181

5. DMA ................................................................................................................................ 183

5.1 Functional Overview ................................................................................................ 183

5.1.1 General Usage ................................................................................................. 183

5.1.2 Auto Power Down .......................................................................................... 184

5.1.3 Priority ............................................................................................................ 184

5.1.4 Hardware Handshake / Hardware Triggering ................................................. 184

6. BLE Module .................................................................................................................... 185

6.1 Functional Overview ................................................................................................ 185

Apollo3 Blue MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A3-0p11p0 Page 4 of 915 2020 Ambiq Micro, Inc.

6.1.1 Introduction ..................................................................................................... 185

6.1.2 Main Features ................................................................................................. 185

6.2 Functional Description ............................................................................................. 186

6.2.1 Data Transfers ................................................................................................. 186

6.3 BLEIF Registers ...................................................................................................... 187

6.3.1 Register Memory Map .................................................................................... 188

6.3.2 BLEIF Registers ............................................................................................. 190

7. MSPI Master Module ....................................................................................................... 223

7.1 Functional Overview ................................................................................................ 223

7.2 Configuration ........................................................................................................... 224

7.3 PIO Operations ........................................................................................................ 225

7.4 DMA Operations ...................................................................................................... 226

7.5 Execute in Place (XIP) Operations .......................................................................... 227

7.5.1 XIP Operation ................................................................................................. 228

7.5.2 Optimized XIP Addressing ............................................................................. 228

7.5.3 Micron XIP Support ........................................................................................ 228

7.6 Command Queueing (CQ) ....................................................................................... 229

7.6.1 Command Queue Data Format ....................................................................... 229

7.6.2 CQ Interrupts .................................................................................................. 230

7.6.3 Pausing CQ Operations ................................................................................... 230

7.6.4 Using the CQ Index registers .......................................................................... 231

7.6.5 MSPI and IOM Intercommunication .............................................................. 232

7.7 Data Scrambling ...................................................................................................... 232

7.8 Auto Power Down ................................................................................................... 233

7.9 Pad Configuration and Enables ................................................................................ 233

7.9.1 Internal Pin Muxing Options .......................................................................... 234

7.9.2 MSPI Pin Timing Board/Package Considerations .......................................... 235

7.10 MSPI Registers ...................................................................................................... 236

7.10.1 Register Memory Map .................................................................................. 237

7.10.2 MSPI Registers ............................................................................................. 238

8. I2C/SPI Master Module ................................................................................................... 265

8.1 Functional Overview ................................................................................................ 265

8.1.1 Main Features ................................................................................................. 266

8.2 Functional Description ............................................................................................. 266

8.2.1 Power Control ................................................................................................. 266

8.2.2 Clocking and Resets ........................................................................................ 267

8.2.3 FIFO ................................................................................................................ 269

8.2.4 Data Alignment ............................................................................................... 270

8.2.5 Transaction Initiation ...................................................................................... 272

8.2.6 Command Queue ............................................................................................ 273

8.3 Programmer’s Reference ......................................................................................... 276

8.4 Interface Clock Generation ...................................................................................... 276

8.5 Command Operation ................................................................................................ 277

8.6 FIFO ......................................................................................................................... 278

8.7 I2C Interface ............................................................................................................ 278

8.7.1 Bus Not Busy .................................................................................................. 278

Apollo3 Blue MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A3-0p11p0 Page 5 of 915 2020 Ambiq Micro, Inc.

8.7.2 Start Data Transfer .......................................................................................... 278

8.7.3 Stop Data Transfer .......................................................................................... 279

8.7.4 Data Valid ....................................................................................................... 279

8.7.5 Acknowledge .................................................................................................. 279

8.7.6 I2C Slave Addressing ..................................................................................... 279

8.7.7 I2C Offset Address Transmission ................................................................... 280

8.7.8 I2C Write Operation with Address Offset ...................................................... 280

8.7.9 I2C Read Operation with Address Offset ....................................................... 281

8.7.10 I2C Write Operation with No Address Offset .............................................. 281

8.7.11 I2C Read Operation with No Address Offset ............................................... 282

8.7.12 Holding the Interface with CONT ................................................................ 282

8.7.13 I2C Multi-master Arbitration ........................................................................ 282

8.8 SPI Operations ......................................................................................................... 282

8.8.1 SPI Configuration ........................................................................................... 282

8.8.2 SPI Slave Addressing ...................................................................................... 283

8.8.3 SPI Write with Address Offset ....................................................................... 283

8.8.4 SPI Read with Address Offset ........................................................................ 283

8.8.5 SPI Write with No Address Offset ................................................................. 284

8.8.6 SPI Read with No Address Offset .................................................................. 284

8.8.7 SPI 3-wire Mode ............................................................................................. 285

8.8.8 Complex SPI Operations ................................................................................ 285

8.8.9 SPI Polarity and Phase .................................................................................... 285

8.9 Bit Orientation ......................................................................................................... 286

8.10 SPI Flow Control ................................................................................................... 286

8.11 Minimizing Power ................................................................................................. 288

8.12 IOM Registers ........................................................................................................ 288

8.12.1 Register Memory Map .................................................................................. 290

8.12.2 IOM Registers ............................................................................................... 295

9. I2C/SPI Slave Module ..................................................................................................... 332

9.1 Functional Overview ................................................................................................ 332

9.2 Local RAM Allocation ............................................................................................ 332

9.3 Direct Area Functions .............................................................................................. 333

9.4 FIFO Area Functions ............................................................................................... 336

9.5 Rearranging the FIFO .............................................................................................. 337

9.6 Interface Interrupts ................................................................................................... 338

9.7 Command Completion Interrupts ............................................................................ 339

9.8 Host Address Space and Registers ........................................................................... 339

9.9 I2C Interface ............................................................................................................ 339

9.9.1 Bus Not Busy .................................................................................................. 340

9.9.2 Start Data Transfer .......................................................................................... 340

9.9.3 Stop Data Transfer .......................................................................................... 340

9.9.4 Data Valid ....................................................................................................... 340

9.9.5 Acknowledge .................................................................................................. 340

9.9.6 Address Operation .......................................................................................... 341

9.9.7 Offset Address Transmission .......................................................................... 341

9.9.8 Write Operation .............................................................................................. 342

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