Wishbone总线协议B4

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Wishbone B4

WISHBONE System-on-Chip (SoC)Interconnection

Architecturefor Portable IP Cores

Brought to You By OpenCores

Wishbone B4

Stewardship

Stewardship for this specification is maintained by OpenCores Organization (hereafter

OpenCores). Questions, comments and suggestions about this document are welcome and

should be directed to:

Richard Herveille, OpenCores Organization

E-MAIL: rherveille@opencores.org URL: www.opencores.org

OpenCores maintains this document to provide an open, freely useable interconnect

architecture for its own and others’ IP-cores. These specifications are intended to

guarantee compatibility between compliant IP-cores and to improve cooperation among

different users and suppliers.

Notice is hereby given that this document is not copyrighted, and has been placed into the

public domain. It may be freely copied and distributed by any means.

The name ‘WISHBONE’ and the ‘WISHBONE COMPATIBLE’ rubber stamp logo are

hereby placed into the public domain (within the scope of System-on-Chip design, System-

on-Chip fabrication and related areas of commercial use). The WISHBONE logo may be

freely used under the compatibility conditions stated elsewhere in this document.

This specification may be used for the design and production of System-on-Chip (SoC)

components without royalties or other financial obligations to OpenCores.

The author(s) of this specification are not aware that the information contained herein, nor

of products designed to the specification, cause infringement on the patent, copyright,

trademark or trade secret rights of others. However, there is a possibility that such

infringement may exist without their knowledge. The user of this document assumes all

responsibility for determining if products designed to this specification infringe on the

intellectual property rights of others.

Disclaimers

In no event shall OpenCores or any of the contributors be liable for any direct, indirect,

incidental, consequential, exemplary, or special damages (including, but not limited to

procurement of substitute goods or services; loss of use, data, or profits; or business

interruption) resulting in any way from the use of this specification. By adopting this

specification, the user assumes all responsibility for its use.

This is a preliminary document, and is subject to change.

Verilog is a registered trademark of Cadence Design Systems, Inc.

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Page 3 / 128

Wishbone B4
Table of Contents
Chapter 1.Introduction                                                                  ______________________________   8  
1 WISHBONE Features                                                                               _________________________________________   9  
2 WISHBONE Objectives                                                                          _______________________________________   10   
3 Specification Terminology                                                                      ____________________________________   12   
4 Use of Timing Diagrams                                                                        _____________________________________   13   
5 Signal Naming Conventions                                                                   ___________________________________   14   
6 WISHBONE Logo                                                                                  ___________________________________________   15   
7 Glossary of Term                                                                                  ___________________________________________   15   
8 References                                                                                           ________________________________________________   24   
Chapter 2.Interface Specification                                               _____________________   25   
1 Required Documentation for IP Cores                                                     ___________________________   25   
1.1 General Requirements for the WISHBONE DATASHEET                                _______________   25   
1.2 Signal Naming                                                                                        _______________________________________________   26   
1.3 Logic Levels                                                                                            _________________________________________________   26   
2 WISHBONE Signal Description                                                               ________________________________   27   
2.1 SYSCON Module Signals                                                                           _______________________________________   27   
2.2 Signals Common to MASTER and SLAVE Interfaces                                     __________________   27   
2.3 MASTER Signals                                                                                      _____________________________________________   28   
2.4 SLAVE Signals                                                                                         _______________________________________________   29   
Chapter 3.WISHBONE Classic Bus Cycles                                    _______________   31   
1 General Operation                                                                                __________________________________________   31   
1.1 Reset Operation                                                                                      _____________________________________________   31   
1.2 Transfer Cycle initiation                                                                            ________________________________________   33   
1.3 Handshaking Protocol                                                                              _________________________________________   33   
1.4 Use of [STB_O]                                                                                       ______________________________________________   37   
1.5 Use of [ACK_O], [ERR_O] and [RTY_O]                                                     ___________________________   38   
1.6 Use of TAG TYPES                                                                                   ____________________________________________   38   
2 SINGLE READ / WRITE Cycles                                                                _________________________________   39   
2.1 Classic standard SINGLE READ Cycle                                                         _____________________________   40   
2.2 Classic pipelined SINGLE READ Cycle                                                        _____________________________   41   
2.3 Classic standard SINGLE WRITE Cycle                                                       ____________________________   43   
2.4 Classic pipelined SINGLE WRITE Cycle                                                       ____________________________   45   
3 BLOCK READ / WRITE Cycles                                                                 _________________________________   47   
3.1 BLOCK READ Cycle                                                                                  ___________________________________________   48   
3.2 BLOCK WRITE Cycle                                                                                __________________________________________   52   
4 RMW Cycle                                                                                           ________________________________________________   56   
5 Data Organization                                                                                 __________________________________________   58   
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Copyright © 2010 OpenCores
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