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首页ML505/ML506/ML507 Reference Design
This user guide introduces several designs that demonstrate Virtex®-5 FPGA features using the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms (referred to collectively as the ML50x boards in this guide). The provided designs include processing systems based on the embedded PowerPC® 440 processor block, the MicroBlazeTM soft processor, the integrated Tri-mode Ethernet MAC, and the RocketIOTM GTP or GTX transceiver.
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ML505/ML506/M
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ML505/ML506/ML507
Reference Design
User Guide
UG349 (v3.1) June 23, 2009
ML505/ML506/ML507 Reference Design www.xilinx.com UG349 (v3.1) June 23, 2009
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development
of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,
without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves
the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors
contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with
technical support or assistance that may be provided to you in connection with the Information.
THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER
WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY
RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL
DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.
© 2007-2009 Xilinx, Inc. All rights reserved.
XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PCI, PCI-SIG,
PCI EXPRESS, PCIE, PCI-X, PCI HOT PLUG, MINI PCI, EXPRESSMODULE, and the PCI, PCI-X, PCI HOT PLUG, and MINI PC design
marks are trademarks, registered trademarks, and/or service marks of PCI-SIG. All other trademarks are the property of their respective
owners.
Revision History
The following table shows the revision history for this document.
Date Version Revision
01/16/07 1.0 Initial Xilinx release.
01/17/07 1.0.1 Minor typographical edit.
05/07/07 2.0 Added support for ML506 boards.
07/24/07 2.1 Updated “EDK Design” section.
09/25/07 2.2 Added “Memory Interface Generator (MIG) Design” section and updated “References”
section.
04/04/08 2.3 Removed SGMII design. Added lwIP demonstration.
05/19/08 3.0 Added support for ML507 boards.
06/27/08 3.0.1 Updated links in “References.”
06/23/09 3.1 Updated Table 1, page 11 and “Reference Designs”section to match changes in designs.
Added “System Monitor”section. Fixed links.
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ML505/ML506/ML507 Reference Design www.xilinx.com 3
UG349 (v3.1) June 23, 2009
Preface: About This Guide
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ML505/ML506/ML507 Reference Design
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
EDK Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MicroBlaze Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PowerPC 440 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stand-Alone Software Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ChipScope Pro Serial I/O Toolkit IBERT Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory Interface Generator (MIG) Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LogiCORE Endpoint Block Plus for PCI Express (x1) Design . . . . . . . . . . . . . . . . . . . . 18
System Generator for DSP Design (ML506) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
System Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table of Contents
ML505/ML506/ML507 Reference Design www.xilinx.com 5
UG349 (v3.1) June 23, 2009
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Preface
About This Guide
This user guide introduces several designs that demonstrate Virtex®-5 FPGA features
using the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms (referred to
collectively as the ML50x boards in this guide). The provided designs include processing
systems based on the embedded PowerPC® 440 processor block, the MicroBlaze™ soft
processor, the integrated Tri-mode Ethernet MAC, and the RocketIO™ GTP or GTX
transceiver.
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/virtex5
.
• Virtex-5 Family Overview
The features and product selection of the Virtex-5 family are outlined in this overview.
• Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 family.
• Virtex-5 FPGA User Guide
Chapters in this user guide cover the following topics:
♦ Clocking Resources
♦ Clock Management Technology (CMT)
♦ Phase-Locked Loops (PLLs)
♦ Block RAM
♦ Configurable Logic Blocks (CLBs)
♦ SelectIO™ Resources
♦ SelectIO Logic Resources
♦ Advanced SelectIO Logic Resources
• Virtex-5 FPGA RocketIO GTP Transceiver User Guide
This guide describes the RocketIO GTP transceivers available in the Virtex-5 LXT and
SXT platforms.
• Virtex-5 FPGA RocketIO GTX Transceiver User Guide
This guide describes the RocketIO GTX transceivers available in the Virtex-5 FXT
platform.
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