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understanding BITSLIP (one more time)
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11-17-2010 07:57 AM - edited 12-16-2010 11:29 PM
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Registered: 07-21-2009
understanding BITSLIP (one more time)
UPDATED 02-dec-2010: Replaced all references to DIVCLK with CLKDIV. Both terms are used in UG382 (Clocking Resources), but
only CLKDIV is used in UG381 (SelectIO Resources) and DS162 (Datasheet). All my other posts in this thread have been updated as
well.
This is my latest attempt to make sense of the Spartan 6 ISERDES2 BITSLIP function. It probably isn't all that complicated, but its
simplicity is obscured by inconsistencies and omissions in the Xilinx documentation, plus Xilinx' reluctance to provide details of the
BITSLIP function logic. Even the webcase support on BITSLIP function has been clouded by an uneven understanding of the function
by the support team. Roy (as in roym) has an understanding of ISERDES2 and BITSLIP which is as deep and thorough as anyone
else I've engaged on the Xilinx team.
So, here is my unofficial and unsanctioned description of the BITSLIP function.
Comments, additions, corrections, and questions are welcome.
- Bob Elkind
Diagrams:
my corrections (markups) to UG381 Figure 3-1:
My attempt at reverse-engineering the BITSLIP 'black box':
My markups and corrections to UG381 Figure 3-2 (not very useful, but it corrects some misinformation)
UPDATED 23-Nov Changed lines 3,5,7, & 9 to make bit numbering and ordering consistent with Fig 3-1:
OK, now for the text (BITSLIP 101):
Word framing of deserialised data can be slow and resource-hungry when implemented in the parallel (word) domain. If implemented
in the bit-serial domain, word framing can be extremely compact. The ISERDES2 block has provisions for word framing in the serial
domain, within the ISERDES2 block. This feature is called BITSLIP.
First, let's describe the problem of word framing at bit-serial data rates. Input serial data streams up to 1Gb/sec (per pin) are
supported by Spartan 6. The IO logic which supports such data rates requires a matching high-frequency clock, called IOCLK, which
is derived from the serial input signals to the FPGA. To handle thes high data rates, the Spartan 6 IO circuitry is designed to operate
at much higher frequencies than the bulk of the FPGA logic (i.e. the fabric). The upper limit for fabric clock frequency is much lower
than the IOCLK frequency limit. Data decoders, used for detecting proper word framing in parallel data words, are built in the (slower)
FPGA fabric logic. Constrained to operating at fabric clock speed, word framing logic often cannot directly control the serial-rate logic
in the IO section. Word framing logic needs some help to control the deserialiser blocks.
The BITSLIP function includes logic to accept a control signal generated in the FPGA fabric by parallel word logic running at parallel
word clock rates. Inside the BITSLIP function, the slow input control signal is synchronised to the IOCLK (bit rate) clock, and is used
to accomplish word framing.
To see how BITSLIP works, first look at the ISERDES2 block diagram (Fig 3-1). Register B is nothing more than a single IOCLK delay
register fed by serial-bit-rate shift register Register A. When the BITSLIP function is enabled (see UG381 Table 3-2, ISERDES2
Attributes), however, Register B becomes register which samples new data only once every N clock cycles (where N is the parallel
word bit-width of the ISERDES2 output). This slows the output of Register B to word-rate (rather than bit-rate).
If Register B samples precisely on word boundaries, the output of Register B will be correctly word-framed. BITSLIP is designed to
delay the update of Register B, under fabric (user logic) control, until the output of Register B is correctly word-framed.
To see how BITSLIP manages the update of Register B, now look at the Functional Diagram of ISERDES2 BITSLIP function. The
output of the BITSLIP function is the clock enable for ISERDES2 Register B. When the clock enable is asserted, Register B inputs are
sampled. When the clock enable is de-asserted, Register B does not change. The Modulo N counter in the diagram counts at IOCLK
rate, from 0 to N-1. When the counter value is 0, the Register B clock enable is asserted. The counter wraps around from (N-1) to 0,
and Register B updates once per N clock cycles -- once per word.
This is all well and good as long as the BITSLIP clock enable output (and Register B input sampling) coincides with the boundary from
one data word to the next. Otherwise, the timing of the BITSLIP output clock enable must somehow be changed to align with data
word boundaries. The rest of the BITSLIP logic allows the BITSLIP control input to delay the clock enable output under fabric control,
until the clock enable output occurs at the correct word boundary (and word framing will be correct).
To shift the position of the clock enable output, fabric logic asserts the BITSLIP control input. Inside the BITSLIP block, the BITSLIP
input is sampled on the rising edge of CLKDIV. CLKDIV is a word-rate clock, and is presumed to be a copy of the fabric clock which
generates the BITSLIP control input. Because the BITSLIP control input is sampled by CLKDIV inside the BITSLIP block, the timing
requirements for the BITSLIP input are very modest. The minimum required setup and hold times, referenced to the CLKDIV rising
edge, are listed in the Spartan 6 datasheet DS162.
Inside the BITSLIP block, the sampled BITSLIP control input is then ANDed with a positive CLKDIV edge detection, and re-sampled at
IOCLK frequency. This re-sampled control is used to insert one (and only one) extra IOCLK clock cycle in the Modulo [N or N+1] word
cycle. The Modulo [N or N+1] counter takes N+1 (instead of N) IOCLK cycles to complete a full cycle. This delays the BITSLIP clock
enable output (to Register B) one IOCLK cycle, and effectively shifts the output of Register B a single bit position left. If the BITSLIP
control input remains asserted for a second CLKDIV rising edge, the word framing will shift again. After N-1 shifts, the result will be
the same as a single bit-position shift to the right. After N shifts, the result will be the same as 0 shifts (no change).
The assertion of the BITSLIP control signal will allow the word framing to change by only one bit position, no more than once per word.
To sum, BITSLIP performs word framing very compactly, at the cost of a handful of FFs and gates. By comparison, a fabric word
frame design requires an NxN barrel shifter, consuming considerably more logic and interconnect resources than the BITSLIP design
to perform an equivalent function.
- Bob Elkind
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