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REALTEK,5口千兆交换机。RTL8367S-CG_Datasheet_v.Pre-0.94.pdf
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RTL8367S-CG
LAYER 2 MANAGED 5+2-PORT
10/100/1000M SWITCH CONTROLLER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. Pre-0.94
11 Jan 2016
Track ID: xxxx-xxxx-xx
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8367S
Datasheet
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller ii Track ID: xxxx-xxxx-xx Rev. Pre-0.94
COPYRIGHT
©2015 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8367S IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary
Pre-0.9 2015/08/06 Preliminary release.
Pre-0.91 2015/08/18 1. Revised Section 6. Pin Assignments
2. Revised Section 6.2. Pin Assignments Table
3. R
e
vi
sed Section 7.3. General Purpose Interfaces
4. Revi
sed Section 7.5. Configuration Strapping Pins
5. R
e
vi
sed Section 7.6. Management
6. Revi
sed Section 7.7. Miscellaneous Pins
Pre-0.92 2015/11/18 1. Revised Section 6. Pin Assignments
2. Revised Section 6.2. Pin Assignments Table
3. Revi
sed Section 7.3. General Purpose Interfaces
4. Revi
sed Section 7.5. Configuration Strapping Pins
5. Revi
sed Section 7.6. Management Interface Pins
6. R
e
vi
sed Section 7.7. Miscellaneous Pins
7. Revi
sed Section 9.19. LED Indicators
8. Revi
sed Section 12.2. Recommended Operating Range
9. A
d
d
Section 12.5.7. HSGMII Characteristics
10. Ad
d Section 12.5.8. SGMII Characteristics
RTL8367S
Datasheet
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller iii Track ID: xxxx-xxxx-xx Rev. Pre-0.94
Revision Release Date Summary
Pre-0.93 2015/12/30 1. Revised Section 12.2. Recommended Operating Range
2. Revised Section 12.3.1. Assembly Description
3. R
e
vised Section 12.3.2. Material Properties
4. Re
vised Section 12.3.3. Simulation Conditions
5. R
e
vised Section 12.3.4. Thermal Performance of LQFP-128 on PCB Under Still
Air Co
nvection
6. Delete Section 12.3.5. Thermal Performance of LQFP-128 on PCB Under Forced
Co
nv
ection
Pre-0.94 2016/01/11 1. Revised Section 12.5.2. EEPROM SMI Slave Mode Timing Characteristics
RTL8367S
Datasheet
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller iv Track ID: xxxx-xxxx-xx Rev. Pre-0.94
Table of Contents
1. GENERAL DESCRIPTION..............................................................................................................................................1
2. FEATURES.........................................................................................................................................................................3
3. SYSTEM APPLICATIONS...............................................................................................................................................5
4. APPLICATION EXAMPLES ...........................................................................................................................................5
4.1. 5-PORT 1000BASE-T SWITCH ......................................................................................................................................5
4.2. 5-PORT 1000BASE-T ROUTER WITH SGMII/HSGMII AND/OR MII/RGMII ................................................................6
5. BLOCK DIAGRAM...........................................................................................................................................................7
6. PIN ASSIGNMENTS .........................................................................................................................................................8
6.1. PACKAGE IDENTIFICATION...........................................................................................................................................8
6.2. PIN ASSIGNMENTS TABLE ............................................................................................................................................9
7. PIN DESCRIPTIONS.......................................................................................................................................................12
7.1. MEDIA DEPENDENT INTERFACE PINS.........................................................................................................................12
7.2. HIGH SPEED SERIAL INTERFACE PINS ........................................................................................................................13
7.3. GENERAL PURPOSE INTERFACES................................................................................................................................13
7.3.1. RGMII Pins...........................................................................................................................................................15
7.3.2. MII Pins................................................................................................................................................................16
7.4. LED PINS...................................................................................................................................................................18
7.5. CONFIGURATION STRAPPING PINS .............................................................................................................................19
7.5.1. Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF)......................................................20
7.6. MANAGEMENT INTERFACE PINS ................................................................................................................................21
7.7. MISCELLANEOUS PINS ...............................................................................................................................................21
7.8. TEST PINS ..................................................................................................................................................................23
7.9. POWER AND GND PINS ..............................................................................................................................................23
8. PHYSICAL LAYER FUNCTIONAL OVERVIEW......................................................................................................24
8.1. MDI INTERFACE ........................................................................................................................................................24
8.2. 1000BASE-T TRANSMIT FUNCTION ...........................................................................................................................24
8.3. 1000BASE-T RECEIVE FUNCTION ..............................................................................................................................24
8.4. 100BASE-TX TRANSMIT FUNCTION...........................................................................................................................24
8.5. 100BASE-TX RECEIVE FUNCTION .............................................................................................................................25
8.6. 10BASE-T TRANSMIT FUNCTION ...............................................................................................................................25
8.7. 10BASE-T RECEIVE FUNCTION ..................................................................................................................................25
8.8. AUTO-NEGOTIATION FOR UTP ..................................................................................................................................25
8.9. CROSSOVER DETECTION AND AUTO CORRECTION.....................................................................................................26
8.10. POLARITY CORRECTION .............................................................................................................................................26
9. GENERAL FUNCTION DESCRIPTION......................................................................................................................27
9.1. RESET ........................................................................................................................................................................27
9.1.1. Hardware Reset....................................................................................................................................................27
9.1.2. Software Reset ......................................................................................................................................................27
9.2. IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................27
9.3. HALF DUPLEX FLOW CONTROL .................................................................................................................................28
9.3.1. Back-Pressure Mode ............................................................................................................................................28
9.4. SEARCH AND LEARNING ............................................................................................................................................29
9.5. SVL AND IVL/SVL ...................................................................................................................................................29
9.6. ILLEGAL FRAME FILTERING .......................................................................................................................................29
9.7. IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL .............................................................................30
RTL8367S
Datasheet
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller v Track ID: xxxx-xxxx-xx Rev. Pre-0.94
9.8. BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL .....................................................................................31
9.9. PORT SECURITY FUNCTION ........................................................................................................................................31
9.10. MIB COUNTERS .........................................................................................................................................................31
9.11. PORT MIRRORING ......................................................................................................................................................31
9.12. VLAN FUNCTION ......................................................................................................................................................32
9.12.1. Port-Based VLAN ............................................................................................................................................32
9.12.2. IEEE 802.1Q Tag-Based VLAN.......................................................................................................................32
9.12.3. Protocol-Based VLAN .....................................................................................................................................33
9.12.4. Port VID ..........................................................................................................................................................33
9.13. QOS FUNCTION ..........................................................................................................................................................34
9.13.1. Input Bandwidth Control .................................................................................................................................34
9.13.2. Priority Assignment .........................................................................................................................................34
9.13.3. Priority Queue Scheduling...............................................................................................................................34
9.13.4. IEEE 802.1p/Q and DSCP Remarking ............................................................................................................35
9.13.5. ACL-Based Priority .........................................................................................................................................35
9.14. IGMP & MLD SNOOPING FUNCTION.........................................................................................................................36
9.15. IEEE 802.1X FUNCTION.............................................................................................................................................37
9.15.1. Port-Based Access Control..............................................................................................................................37
9.15.2. Authorized Port-Based Access Control ...........................................................................................................37
9.15.3. Port-Based Access Control Direction..............................................................................................................37
9.15.4. MAC-Based Access Control.............................................................................................................................37
9.15.5. MAC-Based Access Control Direction ............................................................................................................38
9.15.6. Optional Unauthorized Behavior.....................................................................................................................38
9.15.7. Guest VLAN .....................................................................................................................................................38
9.16. IEEE 802.1D FUNCTION ............................................................................................................................................38
9.17. EMBEDDED 8051........................................................................................................................................................38
9.18. REALTEK CABLE TEST (RTCT) .................................................................................................................................39
9.19. LED INDICATORS.......................................................................................................................................................39
9.20. GREEN ETHERNET......................................................................................................................................................41
9.20.1. Link-On and Cable Length Power Saving .......................................................................................................41
9.20.2. Link-Down Power Saving ................................................................................................................................41
9.21. IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ...............................................................................41
9.22. INTERRUPT PIN FOR EXTERNAL CPU.........................................................................................................................41
10. INTERFACE DESCRIPTIONS .................................................................................................................................42
10.1. EEPROM SMI HOST TO EEPROM ...........................................................................................................................42
10.2. EEPROM SMI SLAVE FOR EXTERNAL CPU..............................................................................................................43
10.3. GENERAL PURPOSE INTERFACE..................................................................................................................................44
10.3.1. Extension Ports RGMII Mode Interface (1Gbps) ............................................................................................45
10.3.2. Extension Ports MII MAC/PHY Mode Interface (10/100Mbps) ......................................................................45
11. REGISTER DESCRIPTIONS ....................................................................................................................................48
11.1. PCS REGISTER (PHY 0~4).........................................................................................................................................48
11.2. REGISTER 0: CONTROL...............................................................................................................................................49
11.3. REGISTER 1: STATUS ..................................................................................................................................................50
11.4. REGISTER 2: PHY IDENTIFIER 1 .................................................................................................................................51
11.5. REGISTER 3: PHY IDENTIFIER 2 .................................................................................................................................51
11.6. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT .................................................................................................51
11.7. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY.......................................................................................52
11.8. REGISTER 6: AUTO-NEGOTIATION EXPANSION ..........................................................................................................53
11.9. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER..................................................................................53
11.10. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ............................................................54
11.11. REGISTER 9: 1000BASE-T CONTROL REGISTER ....................................................................................................54
11.12. REGISTER 10: 1000BASE-T STATUS REGISTER .....................................................................................................55
11.13. REGISTER 15: EXTENDED STATUS.........................................................................................................................55
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