Proposed IEEE Standard P1450 - Review Document
STIL Language Manual 0.23 Page 3 5/21/96
Prologue
The STIL language has initially been developed by an ad-hoc consortium of test equipment ven-
dors, CAE and CAD vendors, and IC manufacturers, to address the lack of a common solution for
transferring digital test data from the generation environment to the test equipment. The following
two sections are excerpts from the IEEE PAR documentation to provide an orientation on the
foundation of this language. The third section identifies some aspects of test that were eliminated
from consideration for this current standard.
0.1 Orientation / Goal of the STIL Standard
This project is to define a standard language that:
a) Facilitates the transfer of large volumes of digital test information from Computer-Aided Engi-
neering (CAE) environments to Automated Test Equipment (ATE) environments;
b) Specifies pattern, format, and timing information sufficient to define the application of test vec-
tors to a Device Under Test (DUT);
c) Supports the volume of bulk test information generated from structured test such as scan/Auto-
matic Test Pattern Generation (ATPG), integral test techniques such as Built-In Self Test (BIST),
and functional test specification, for Integrated Circuit designs and their Assemblies, in a format
optimized for application in Automated Test Equipment (ATE) environments.
0.2 Purpose of the STIL Standard
Existing CAE tools have unique and differing software output interfaces which are not portable
into the unique and proprietary IC ATE input interfaces. Third party support environments have
not kept pace with the test requirements of VLSIC device and test data generated from structured
test (such as ATPG) or integral test techniques such as BIST. Definition of a standard to support
representation of this data in an efficient optimal format is beneficial to three parties: the CAE
vendors who must create this data, the IC vendors who must support and manipulate this data, and
the ATE vendors who must accept this data.
With a common standard between CAE and IC ATE environments, the generation, movement,
and processing of this test data is greatly facilitated. This standard also allows for immediate
access to test equipment supporting this standard, which benefits both ATE vendors and IC ven-
dors reviewing this equipment.
This standard will finally serve as a catalyst for the development of a set of standard third party
interface tools to both test and design aspects of IC device generation.
0.3 Some of What the STIL Standard is NOT
In setting the scope for any standard, some issues are defined to not be pertinant to the initial
project. The following list is a partial set of issues that were dropped from the scope of this initial
project, with a note as to why the issue was dropped. Any future revision of the standard is open
to extensions in all of these areas.
• Levels: a key aspect of a digital test program is the ability to establish voltage (and
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