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Design Compiler
®
Reference Manual: Register
Retiming
Version B-2008.09, September 2008
ii
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Design Compiler Reference Manual: Register Retiming, version B-2008.09
iii
Contents
What’s New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
1. Introduction to Register Retiming
Understanding Register Retiming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
A Register Retiming Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Design Flow Using Register Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Register Retiming Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
The optimize_registers Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
The pipeline_design Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
The balance_registers Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
2. Register Retiming Concepts
Basic Definitions and Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Flip-Flops and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
SEQGENs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Control Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Register Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Forward Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Backward Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Asynchronous Control Inputs of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
iv
Synchronous Control Inputs of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Translating Synchronous Input Pins to Equivalent SEQGEN Pins . . . . . . . . . . 2-9
Transforming Synchronous Input Pins Through Combinational
Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Multiclass Retiming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Pipeline and Nonpipeline Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Reset State Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
3. Writing HDL Code for Retiming
Allowed Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Writing HDL Code for Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Calculating the Number of Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Determining the Initial Location of the Registers . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Writing HDL Code for Nonpipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
4. Performing Analysis and Elaboration for Retiming
Inferring Sequential Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Inferring Registers for Pipelines and Nonpipelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
5. Setting Attributes and Constraints for Retiming
Setting the dont_touch Attribute on SEQGEN Cells . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Setting the dont_touch Attribute for Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Setting the dont_touch Attribute for Nonpipelines . . . . . . . . . . . . . . . . . . . . . . . 5-2
Setting Area Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Setting Area Constraints for Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Setting Area Constraints for Nonpipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Setting Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Setting Timing Constraints for Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Setting Timing Constraints for Nonpipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Netlist Modifications to Avoid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Test-Related Modifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Physical Design-Related Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
v
6. Retiming the Mapped Netlist
Preventing Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Removing dont_touch Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Setting Area Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Doing Timing Analysis During Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Setting Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Selecting Transformation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Recommended Transformation Options for Pipelines . . . . . . . . . . . . . . . . . . . . 6-7
Recommended Transformation Options for Nonpipelines . . . . . . . . . . . . . . . . . 6-8
Retiming Designs With Multiple Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Settings That Influence Register Retiming Runtime . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Netlist Changes Performed by Register Retiming. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
7. Analyzing Retiming Results
Standard Output of the optimize_registers Command . . . . . . . . . . . . . . . . . . . . . . . 7-2
Checking for Design Features That Limit the Quality of Results. . . . . . . . . . . . . . . . 7-2
Output Before Registers Are Moved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Output After Registers Are Moved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Displaying the Sequence of Cells That Limits Delay Optimization . . . . . . . . . . . . . . 7-5
8. Pipelining Combinational Designs
Summary of the pipeline_design Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Comparing the pipeline_design and optimize_registers Commands . . . . . . . . . . . . 8-2
Design Flow Using the pipeline_design Command . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Appendix A. Additional Information on the Register Retiming Commands
Setting Retiming Attributes on Individual Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Other Commands Related to Retiming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Examples of dc_shell Register Retiming Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
Script for a Nonpipelined Design, Using the optimize_registers Command . . . A-4
Script for a Pipelined Design, Using the optimize_registers Command. . . . . . . A-4
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