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BCM2837-ARM-Peripherals_.pdf
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BCM2837数据手册 树莓派3B 的CPU的资料 BCM2837 ARM Peripherals BCM2837 ARM Peripherals BCM2837 ARM Peripherals BCM2837 ARM Peripherals
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BCM2837 ARM Peripherals
© 2012 Broadcom Corporation.
All rights reserved
Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW
Table of Contents
1 Introduction 5
1.1 Overview 5
1.2 Address map 5
1.2.1 Diagrammatic overview 5
1.2.2 ARM virtual addresses (standard Linux kernel only) 9
1.2.3 ARM physical addresses 9
1.2.4 Bus addresses 9
1.3 Peripheral access precautions for correct memory ordering 10
2 Auxiliaries: UART1 & SPI1, SPI2 11
2.1 Overview 11
2.1.1 AUX registers 13
2.2 Mini UART 14
2.2.1 Mini UART implementation details 15
2.2.2 Mini UART register details 15
2.3 Universal SPI Master (2x) 26
2.3.1 SPI implementation details 26
2.3.2 Interrupts 27
2.3.3 Long bit streams 27
2.3.4 SPI register details 28
3 BSC 34
3.1 Introduction 34
3.2 Register View 34
3.3 10 Bit Addressing 42
4 DMA Controller 43
4.1 Overview 43
4.2 DMA Controller Registers 44
4.2.1 DMA Channel Register Address Map 45
4.3 AXI Bursts 73
4.4 Error Handling 73
4.5 DMA LITE Engines 74
5 External Mass Media Controller 75
o Introduction 75
o Registers 76
6 General Purpose I/O (GPIO) 103
6.1 Register View 104
6.2 Alternative Function Assignments 116
6.3 General Purpose GPIO Clocks 120
7 Interrupts 123
7.1 Introduction 123
7.2 Interrupt pending 124
7.3 Fast Interrupt (FIQ) 125
7.4 Interrupt priority 125
7.5 Registers 126
8 PCM / I2S Audio 133
8.1 Block Diagram 134
8.2 Typical Timing 134
8.3 Operation 135
8.4 Software Operation 137
8.4.1 Operating in Polled mode 137
8.4.2 Operating in Interrupt mode 137
06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 157
© 2012 Broadcom Corporation. All rights reserved
8.4.3 DMA 123
8.5 Error Handling. 123
8.6 PDM Input Mode Operation 124
8.7 GRAY Code Input Mode Operation 124
8.8 PCM Register Map 125
9 Pulse Width Modulator 138
9.1 Overview 138
9.2 Block Diagram 138
9.3 PWM Implementation 139 9.4 Modes of Operation 139
9.5 Quick Reference 140
9.6 Control and Status Registers 141
10 SPI 148
10.1 Introduction 148
10.2 SPI Master Mode 148 10.2.1 Standard mode 148
10.2.2 Bidirectional mode 149
10.3 LoSSI mode 150
10.3.1 Command write 150
10.3.2 Parameter write 150
10.3.3 Byte read commands 151 10.3.4 24bit read command 151 10.3.5
32bit read command 151
10.4 Block Diagram 152
10.5 SPI Register Map 152
10.6 Software Operation 158
10.6.1 Polled 158
10.6.2 Interrupt 158
10.6.3 DMA 158
10.6.4 Notes 159
11 SPI/BSC SLAVE 160
11.1 Introduction 160
11.2 Registers 160
12 System Timer 172
12.1 System Timer Registers 172
13 UART 175
13.1 Variations from the 16C650 UART 175 13.2 Primary UART Inputs and Outputs
176
13.3 UART Interrupts 176
13.4 Register View 177
14 Timer (ARM side) 196
14.1 Introduction 196
14.2 Timer Registers: 196
15 USB 200
15.1 Configuration 200
15.2 Extra / Adapted registers. 202
06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page iii
© 2012 Broadcom Corporation. All rights reserved
1 Introduction
1.1 Overview
BCM2835 contains the following peripherals which may safely be accessed by the ARM:
• Timers
• Interrupt controller
• GPIO
• USB
• PCM / I2S
• DMA controller
• I2C master
• I2C / SPI slave
• SPI0, SPI1, SPI2
• PWM
• UART0, UART1
The purpose of this datasheet is to provide documentation for these peripherals in sufficient
detail to allow a developer to port an operating system to BCM2835.
There are a number of peripherals which are intended to be controlled by the GPU. These are
omitted from this datasheet. Accessing these peripherals from the ARM is not recommended.
1.2 Address map
1.2.1 Diagrammatic overview
In addition to the ARM’s MMU, BCM2835 includes a second coarse-grained MMU for
mapping ARM physical addresses onto system bus addresses. This diagram shows the main
address spaces of interest:
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