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RN6862M视频编解码芯片资料
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更新于2023-03-03
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三通道高清视屏解码器,支持CSI2差分输出,可用于AHD转MIPI接口,YUV422输出格式,可编程2bit虚拟通道,每个链路多达3通道720p或2通道1080p或2通道720p+1通道1080p
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Rev. 1.0 – April.2019 Richnex Confidential and Proprietary Page 1 of 48
RN6862M
3-Channel HD Video Decoder with MIPI CSI2 Output
RN6862M
Data Sheet
3-Channel HD Video Decoder
With
MIPI CSI2 Output
(Rev. 1.0)
RICHNEX CONFIDENTIAL AND PROPRIETARY
RICHNEX MICROELECTRONICS CORP.
4F, No.95, Minchiuan Road, Hsintien District,
New Taipei City, Taiwan 23145
T 886-2-86676161
F 886-2-86673131
www.richnex.com
Rev. 1.0 – April.2019 Richnex Confidential and Proprietary Page 2 of 48
RN6862M
3-Channel HD Video Decoder with MIPI CSI2 Output
Revision History
Revision
Date
Notes
0.1
2018-06-19
Initial draft.
0.2
2018-07-24
Added register FEh product ID description
0.3
2018-08-06
Added register 19h description.
1.0
2019-04-10
Modified video format description
Copyright © 2010-2019 by Richnex Microelectronics Corp.
NOTE:
Richnex reserves the right to change the circuitry and/or specifications without notice at any time. Customers
should obtain the latest relevant information and data sheets before placing orders and should verify that such
information is current and complete. Richnex cannot assume responsibility for use of any circuitry other than
circuitry entirely embodied in a Richnex product. Information furnished by Richnex is believed to be accurate and
reliable. However, no responsibility is assumed by Richnex or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Richnex or its subsidiaries.
Rev. 1.0 – April.2019 Richnex Confidential and Proprietary Page 3 of 48
RN6862M
3-Channel HD Video Decoder with MIPI CSI2 Output
Table of Contents
TABLE OF CONTENTS ......................................................................................................... 3
1 GENERAL DESCRIPTION .............................................................................................. 5
2 CONTACT INFORMATION ........................................................................................... 6
3 FEATURES .................................................................................................................. 7
4 BLOCK DIAGRAM ....................................................................................................... 8
5 PIN DIAGRAM ............................................................................................................ 9
6 PIN DESCRIPTIONS ................................................................................................... 10
7 I
2
C ADDRESS SETTING............................................................................................... 13
8 REGISTER MAP ......................................................................................................... 14
8.1 CHIP CONTROL REGISTERS ............................................................................................... 16
8.1.1 Central Control Register........................................................................................... 16
8.1.1.1. Reset / Sleep Control Register ...................................................................... 16
8.1.1.2. Analog Macro Control Register .................................................................... 16
8.1.2 Video Clock Configuration Register ......................................................................... 16
8.1.2.1. Video Clock Configuration A ......................................................................... 16
8.1.2.2. Video Clock Configuration B ......................................................................... 17
8.1.3 Video Data Port Configuration Register .................................................................. 17
8.1.3.1. Video Data Port Configuration A .................................................................. 19
8.1.3.2. Video Data Port Configuration B .................................................................. 20
8.1.3.3. Video Data Port Configuration C ................................................................. 20
8.1.4 GPIO Pin Configuration Register .............................................................................. 21
8.1.4.1. Video Timing Pin Enable Register ................................................................. 21
8.1.4.2. Video Timing Pin Direction Control Register ................................................ 22
8.1.4.3. Video Timing Pin GPIO Register .................................................................... 24
8.1.4.4. Coax33 Pin Control Register ......................................................................... 25
8.1.5 Video Format Selection Register .............................................................................. 25
8.1.6 Product ID, Low Byte ................................................................................................ 26
8.1.7 Product ID, High Byte ............................................................................................... 26
8.1.8 Register Set Selection .............................................................................................. 26
8.2 VIDEO DECODER CONTROL REGISTERS ............................................................................... 27
8.2.1 Mode Control Register ............................................................................................. 27
8.2.2 Brightness Control Register ..................................................................................... 27
8.2.3 Contrast Control Register ........................................................................................ 28
8.2.4 Saturation Control Register ..................................................................................... 28
8.2.5 Hue Control Register ................................................................................................ 28
8.2.6 Enhancement Control Register ................................................................................ 28
Rev. 1.0 – April.2019 Richnex Confidential and Proprietary Page 4 of 48
RN6862M
3-Channel HD Video Decoder with MIPI CSI2 Output
8.2.7 Input Control Register .............................................................................................. 28
8.2.8 Output & Decoder Control Register ......................................................................... 29
8.2.9 Video Detection Control Register ............................................................................ 29
8.2.10 Blue Screen Control Register.................................................................................. 30
8.2.11 Cropping Control Register...................................................................................... 30
8.2.12 ID Insertion Control Register .................................................................................. 30
8.2.13 BT.656/BT656-like Bus Control Register ................................................................ 34
8.2.14 HD Mode Control Registers ................................................................................... 35
8.2.15 Black/White Stretch Control .................................................................................. 36
8.2.16 Coaxitron Control Registers ................................................................................... 36
8.3 MIPI CONTROL REGISTERS .............................................................................................. 37
8.3.1 MIPI CSI-2 Control Registers .................................................................................... 39
8.3.2 MIPI TX Control Registers ........................................................................................ 42
9 ELECTRICAL SPECIFICATIONS .................................................................................... 44
9.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................ 44
9.2 RECOMMENDED OPERATING CONDITIONS .......................................................................... 44
9.3 DC CHARACTERISTICS ..................................................................................................... 44
9.4 POWER CONSUMPTION ................................................................................................... 45
9.5 TWO-WIRE INTERFACE TIMING ......................................................................................... 45
9.6 ANALOG VIDEO PARAMETERS .......................................................................................... 45
10 APPLICATION DIAGRAM ........................................................................................... 47
11 PACKAGE OUTLINES ................................................................................................. 48
12 ORDERING INFORMATION ....................................................................................... 48
Rev. 1.0 – April.2019 Richnex Confidential and Proprietary Page 5 of 48
RN6862M
3-Channel HD Video Decoder with MIPI CSI2 Output
1 General Description
RN6862M is a feature rich, high quality 3-channel HD video decoder chip which integrated 3
high performance ADCs. The associated Clamping and automatic gain control (AGC) circuit hold
the AC coupled signal to a DC level as well as set the signal gain for maximum signal dynamic
range before digitization. The analog front-end (AFE) with automatic gain control (AGC) can
accept an weak input signal and allows signals from the source directly applied to the decoder
input without going through extra gain/attenuation stage. The accurate color carrier phase
acquisition is achieved by the low jitter phase lock loop (PLL).
With an improved and robust sync processing circuit, horizontal and vertical SYNC pulses can be
correctly extracted from D1, 720p, or 1080p signal. Working together with the AFE, very weak or
noisy video signals can be reliably decoded. Variants of NTSC/PAL signals, 720p or 1080p can be
detected automatically, and a comb filter yields the minimum artifacts in performing Y/C
separation. The video post-processing functions such as color space conversion, brightness,
contrast, saturation, and hue control are independently adjustable for each channel via the I
2
C
interface.
RN6862M’s video data port is programmable to transmit in the standard ITU-R BT.656 4:2:2
format for D1 resolution. Higher resolution image, such as 720p or 1080p, can be transmitted
using BT.656-like format. RN6862M also support two MIPI CSI2 output interface.
With a 48-pin, 6mmx6mm QFN package, RN6862M is the best solution for high resolution analog
to digital video conversion applications in terms of functionality, video quality, price, reliability,
and overall customer support. Typical applications of RN6862M include, but not limited to:
standalone security DVR, automobile dash cam and video recorder.
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