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Copyright © 2003-2010 ARM. All rights reserved.
ARM IHI 0022C (ID030510)
AMBA
®
AXI Protocol
Version: 2.0
Specification
ARM IHI 0022C Copyright © 2003-2010 ARM. All rights reserved. ii
ID030510 Non-Confidential
AMBA AXI Protocol
Specification
Copyright © 2003-2010 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
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adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
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This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or
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ARM AMBA Specification Licence
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AMBA SPECIFICATION TO ARM.
“LICENSEE” means You and your Subsidiaries.
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Change history
Date Issue Confidentiality Change
16 June 2003 A Non-Confidential First release
19 March 2004 B Non-Confidential First release of V1.0
03 March 2010 C Non-Confidential First release of V2.0
ARM IHI 0022C Copyright © 2003-2010 ARM. All rights reserved. iii
ID030510 Non-Confidential
(iii) offer to sell, sell, supply or otherwise distribute products which have either been (a) created by or for LICENSEE
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ARM contract references: LEC-PRE-00490-V4.0 ARM AMBA Specification Licence
Confidentiality Status
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Unrestricted Access is an ARM internal classification.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
ARM IHI 0022C Copyright © 2003-2010 ARM. All rights reserved. iv
ID030510 Non-Confidential
Contents
AMBA AXI Protocol Specification
Preface
About this book ............................................................................................................ x
Feedback .................................................................................................................. xiii
Chapter 1 Introduction
1.1 About the AXI protocol ............................................................................................. 1-2
1.2 Architecture .............................................................................................................. 1-4
1.3 Basic transactions .................................................................................................... 1-7
1.4 Additional features ................................................................................................. 1-10
Chapter 2 Signal Descriptions
2.1 Global signals .......................................................................................................... 2-2
2.2 Write address channel signals ................................................................................. 2-3
2.3 Write data channel signals ....................................................................................... 2-4
2.4 Write response channel signals ............................................................................... 2-5
2.5 Read address channel signals ................................................................................. 2-6
2.6 Read data channel signals ...................................................................................... 2-7
2.7 Low-power interface signals .................................................................................... 2-8
Chapter 3 Channel Handshake
3.1 Handshake process ................................................................................................. 3-2
3.2 Relationships between the channels ....................................................................... 3-5
3.3 Dependencies between channel handshake signals ............................................... 3-6
Chapter 4 Addressing Options
4.1 About addressing options ........................................................................................ 4-2
4.2 Burst length .............................................................................................................. 4-3
4.3 Burst size ................................................................................................................. 4-4
Contents
ARM IHI 0022C Copyright © 2003-2010 ARM. All rights reserved. v
ID030510 Non-Confidential
4.4 Burst type ................................................................................................................. 4-5
4.5 Burst address ........................................................................................................... 4-7
Chapter 5 Additional Control Information
5.1 Cache support ......................................................................................................... 5-2
5.2 Protection unit support ............................................................................................. 5-4
Chapter 6 Atomic Accesses
6.1 About atomic accesses ............................................................................................ 6-2
6.2 Exclusive access ..................................................................................................... 6-3
6.3 Locked access ......................................................................................................... 6-6
Chapter 7 Response Signaling
7.1 About response signaling ........................................................................................ 7-2
7.2 Response types ....................................................................................................... 7-3
Chapter 8 Ordering Model
8.1 About the Ordering model ........................................................................................ 8-2
8.2 Transfer ID fields ..................................................................................................... 8-3
8.3 Read ordering .......................................................................................................... 8-4
8.4 Normal write ordering .............................................................................................. 8-5
8.5 Write data interleaving ............................................................................................. 8-6
8.6 Read and write interaction ....................................................................................... 8-7
8.7 Interconnect use of ID fields .................................................................................... 8-8
8.8 Recommended width of ID fields ............................................................................. 8-9
Chapter 9 Data Buses
9.1 About the data buses ............................................................................................... 9-2
9.2 Write strobes ............................................................................................................ 9-3
9.3 Narrow transfers ...................................................................................................... 9-4
9.4 Byte invariance ........................................................................................................ 9-5
Chapter 10 Unaligned Transfers
10.1 About unaligned transfers ...................................................................................... 10-2
10.2 Examples ............................................................................................................... 10-3
Chapter 11 Clock and Reset
11.1 Clock and reset requirements ................................................................................ 11-2
Chapter 12 Low-power Interface
12.1 About the low-power interface ............................................................................... 12-2
12.2 Low-power clock control ........................................................................................ 12-3
Chapter 13 AXI4
13.1 Burst support ......................................................................................................... 13-2
13.2 Quality of service signaling .................................................................................... 13-3
13.3 Multiple region interfaces ....................................................................................... 13-5
13.4 Write response dependencies ............................................................................... 13-6
13.5 AWCACHE and ARCACHE Attributes ................................................................... 13-8
13.6 Ordering requirements for Non-modifiable transactions ...................................... 13-10
13.7 Updated meaning of Read Allocate and Write Allocate ....................................... 13-11
13.8 Memory types ...................................................................................................... 13-14
13.9 Mismatched Attributes ......................................................................................... 13-19
13.10 Transaction buffering ........................................................................................... 13-20
13.11 Use of device memory types ............................................................................... 13-21
13.12 Legacy considerations ......................................................................................... 13-22
13.13 Ordering model .................................................................................................... 13-23
13.14 User signals ......................................................................................................... 13-28
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