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首页台湾交大ESD教程(86页PPT)
台湾交大ESD教程(86页PPT)
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更新于2023-03-03
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ESD Protection Techniques in Deep-Submicron CMOS Technology OUTLINE 1. Models of ESD Events. 2. ESD Specifications for IC Products. 3. Pin Combination in ESD Testing. 4. Design Concept of On-Chip ESD Protection. 5. Process Issues on ESD Robustness. 6. Recent Advances in CMOS On-Chip ESD Protection Techniques. 7. Whole-Chip ESD Protection Scheme. 8. Conclusion and Discussion
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Page 1
1
Ker’2K
ESD Protection Techniques
in Deep-Submicron CMOS Technology
Dr. Ming-Dou Ker
Integrated Circuits & Systems Laboratory
Institute of Electronics
National Chiao-Tung University, Hsinchu, Taiwan
mdker@ieee.org
Sept. 2000
2
Ker’2K
OUTLINE
1. Models of ESD Events.
2. ESD Specifications for IC Products.
3. Pin Combination in ESD Testing.
4. Design Concept of On-Chip ESD Protection.
5. Process Issues on ESD Robustness.
6. Recent Advances in CMOS On-Chip ESD Protection
Techniques.
7. Whole-Chip ESD Protection Scheme.
8. Conclusion and Discussion
3
3
Ker’2K
Models of ESD (Electrostatic Discharge) Events
(1). Human Body Model (HBM)
Standards :
1. MIL-STD-833C Method 3015.7
2. EIA/JESD22-A114-A (JEDEC, 1997)
3. ESD STM 5.1 (EOS/ESD, 1998)
CHBM= 100pF; RHBM= 1.5k
Ω
4
4
Ker’2K
Models of ESD (Electrostatic Discharge) Events
(2). Machine Model (MM)
Standards :
1. EIAJ-IC-121 Method 20
2. EIA/JESD22-A115-A (JEDEC, 1997)
3. ESD STM 5.2 (EOS/ESD, 1999)
CMM= 200pF
RMM= 0
Ω
VESD
Device
Under
TestC=200pF
GND
Rg
5
5
Ker’2K
Models of ESD (Electrostatic Discharge) Events
(3). Charged Device Model (CDM)
Standards :
1. JESD22-C101 (JEDEC, 1997)
2. ESD DS5.3.1 (EOS/ESD, 1996)
CCDM
6
6
Ker’2K
Models of ESD (Electrostatic Discharge) Events
(3). Charged Device Model (CDM)
Different dies and packages cause different ESD voltages in the CDM ESD events.
2
Page 2
7
7
Ker’2K
Models of ESD (Electrostatic Discharge) Events
(3). Charged Device Model (CDM)
GND
VESD
Device
Under
Test
Cd
Rg
Ld
Rd
8
8
Ker’2K
Comparisons among the ESD Models
9
9
Ker’2K
ESD Specifications for IC Products
HBM MM CDM
+/- 2kV +/- 200V +/- 1kV
+/- 4kV +/- 400V +/- 1.5kV
+/- 10kV +/- 1kV +/- 2kV
Okay
Safe
Super
* An IC during ESD test with all pin combinations has to
pass above ESD specifications (both positive and negative
ESD voltages).
Basic Spec. for
Commercial IC’s
10
Ker’2K
Process Issue on ESD Robustness (I)
P-substrate
P-well
N+P+ N+
SourceBulk
Gate
Drain
L
Deep-Submicron CMOS Technologies:
(1). thinner gate oxide
(2). shorter channel length
(3). shallower Drain/Source junction
(4). Lightly-Doped Drain (LDD) structure
(5). Silicide / Salicide
(6). Locos
à
Shallow Trench Isolation (STI)
(7). Epitaxial substrate
(8). SOI
11
Ker’2K
Process Issue on ESD Robustness (II)
LDD and Silicide seriously degrade
ESD robustness of NMOS
Effect of Silicide thickness
on ESD robustness of NMOS
12 12
12
Ker’2K
ESD Current Path in the NMOS with LDD Structure
P-substrate
P-well
N+P+
Gate
Gate
N+
P+
N+
PAD
VESD
+V
Drain
Contact
IESD
IESD
IESD
Rwell
Rwell
3
Page 3
13
Ker’2K
Process Issue on ESD Robustness (III)
Effect of Layout Spacing
on ESD robustness of NMOS
Effect of Channel Length
on ESD robustness of NMOS
14
14
Ker’2K
ESD stress on the input or output pins with the VDD or VSS pins
relatively grounded :
(1) PS-mode (2) NS-mode
(3) PD-mode (4) ND-mode
VESD
0V
+V
VSS
VDD
-V
0V
VESD
VSS
VDD
VESD
0V
+V
VSS
VDD
-V
0V
VESD
VSS
VDD
Pin Combination in HBM / MM ESD Testing (I)
15
Ker’2K
HBM / MM ESD Failure on the I/O Devices
16
16
Ker’2K
Pin-to-Pin ESD Stress :
(1) Positive-mode (2) Negative-mode
VESD
0V
+V
VDD
I/O
VSS
VESD
-V
0V
VDD
I/O
VSS
Pin Combination in HBM / MM ESD Testing (II)
17
17
Ker’2K
Internal ESD Damage Due to Pin-to-Pin ESD Stress
Pin-to-pin ESD stress
easy to cause ESD damage located at the internal circuits.
+V
0V
VSS
Output
Pad
VDD
PMOS
NMOS
Input
PAD
IESD
IESD
IESD
IESD
VESD
Dn1
Dp1
Input ESD
Protection Circuit
Output Buffer
Internal
Circuits
18
18
Ker’2K
VDD-to-VSS ESD Stress :
(1) Positive-mode (2) Negative-mode
VESD
-V
0V
VSS
VDD
VESD
0V
+V
VSS
VDD
Pin Combination in HBM / MM ESD Testing (III)
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