MC68332详细介绍

MC68360

QUad Integrated

Communications Controller

User’s Manual

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liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of

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ii MC68360 USER’S MANUAL MOTOROLA

MOTOROLA MC68360 USER’S MANUAL iii

PREFACE

The complete documentation package for the MC68360 consists of the MC68360UM/AD,

The

Section 2 Signal Descriptions

Section 6 System Integration Module (SIM60)

Section 7 Communication Processor Module (CPM)

Section 8 IEEE 1149.1 Test Access Port

Section 10 Electrical Characteristics

iv MC68360 USER’S MANUAL MOTOROLA

Table of Contents

1.1 QUICC Key Features .............................................................................. 1-1

1.2 QUICC Architecture Overview................................................................. 1-4

1.3.3 Software Compatibility Issues ................................................................. 1-7

1.4 QUICC Glueless System Design............................................................. 1-8

1.5 QUICC Serial Configurations .................................................................. 1-9

1.6 QUICC Serial Configuration Examples ................................................. 1-16

1.7 QUICC System Bus Configurations ...................................................... 1-17

2.1 System Bus Signal Index ........................................................................ 2-1

2.1.1 Address Bus............................................................................................ 2-1

2.1.1.1 Address Bus (A27–A0)............................................................................ 2-1

2.1.4.1 Parity (PRTY0). ....................................................................................... 2-6

2.1.4.2 Parity (PRTY1). ....................................................................................... 2-6

2.1.4.3 Parity (PRTY2). ....................................................................................... 2-6

2.1.4.4 Parity (PRTY3). ....................................................................................... 2-6

2.1.5 Memory Controller................................................................................... 2-6

2.1.5.1 Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0) ................... 2-6

2.1.5.2 Chip Select/Row Address Select/Interrupt Acknowledge (CS7/RAS7/IACK7).

2-6

2.1.5.3 Column Address Select/Interrupt Acknowledge (CAS3–CAS0/IACK6, 3, 2,

1). 2-7

2.1.7.4 Data Strobe (DS)..................................................................................... 2-8