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STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx Flash programming manual STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx Flash 编程用户手册
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December 2010 Doc ID 15687 Rev 2 1/27
PM0059
Programming manual
STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx
Flash programming manual
Introduction
This programming manual describes how to program the Flash memory of STM32F205xx,
STM32F207xx, STM32F215xx and STM32F217xx microcontrollers. For convenience, these
will be referred to as STM32F20x and STM32F21x in the rest of this document unless
otherwise specified.
The STM32F20x and STM32F21x embedded Flash memory can be programmed using in-
circuit programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application
into the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I
2
C, SPI,
etc.) to download programming data into memory. With IAP, the Flash memory can be re-
programmed while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements a prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out Flash memory operations (program/erase).
Program/erase operations can be performed over the whole product voltage range.
Read/write protections and option bytes are also implemented.
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Contents PM0059
2/27 Doc ID 15687 Rev 2
Contents
1 Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Read interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.1 Relation between CPU clock frequency and Flash memory read time . . 8
1.4.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 9
1.5 Erase & program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.1 Unlocking the Flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.2 Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.3 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.4 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.6.1 Description of user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.6.2 Programming user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.3 Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.4 Write protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.7 One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.8 Flash interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.8.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . . 19
1.8.2 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.8.3 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 20
1.8.4 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.8.5 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.8.6 Flash option control register (FLASH_OPTCR) . . . . . . . . . . . . . . . . . . . 23
1.8.7 Flash interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PM0059 List of tables
Doc ID 15687 Rev 2 3/27
List of tables
Table 1. Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . . 8
Table 3. Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Option byte organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. OTP part organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Flash register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
List of figures PM0059
4/27 Doc ID 15687 Rev 2
List of figures
Figure 1. Flash memory interface connection inside system architecture . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Sequential 32-bit instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PM0059
Doc ID 15687 Rev 2 5/27
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
● The CPU core integrates two debug ports:
– JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
– SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols, please refer to the Cortex M3 Technical
Reference Manual
● Word: data/instruction of 32-bit length.
● Half word: data/instruction of 16-bit length.
● Byte: data of 8-bit length.
● Double word: data of 64-bit length.
● IAP (in-application programming): IAP is the ability to reprogram the Flash memory of a
microcontroller while the user program is running.
● ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
● I-Code: this bus connects the Instruction bus of the CPU core to the Flash instruction
interface. Prefetch is performed on this bus.
● D-Code: this bus connects the D-Code bus (literal load and debug access) of the CPU
to the Flash data interface.
● Option bytes: product configuration bits stored in the Flash memory.
● OBL: option byte loader.
● AHB: advanced high-performance bus.
● CPU: refers to the Cortex-M3 core.
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