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How To Successfully Use Gated Clocking
in an
ASIC Design
Darren Jones
MIPS Technologies, Inc.
dj@mips.com
ABSTRACT
Gated clocking is a true silver bullet for hardware designers. Using this technique, engineers can
improve all three major performance metrics of a circuit: speed, area, and power. Unfortunately,
EDA tools have traditionally lacked support for gated clocks. These limitations have relegated
clock gating to the full-custom design community. However, new features in synthesis and static
timing analysis tools have brought gated clocking to mainstream ASIC designers.
This paper discusses the pitfalls that still exist to using gated clocks in an ASIC design.
Furthermore, it suggests methodologies and workarounds that can be used to avoid these
problems so that gated clocking can be used successfully. The paper explains how gated clocking
impacts the following areas: logic synthesis, static timing analysis (STA), automatic test-pattern
generation (ATPG), clock tree synthesis, and standard-cell library design.
SNUG Boston 2002 2 Successful Gated Clocking
1.0 Description of Problem
ASIC designers primarily use positive edge-triggered D flip flops to generate registers and/or
storage elements. These flip flops are clocked every cycle; if they need to hold their previous
value, a recirculating MUX circuit is typically used. Figure 1 shows this circuit.
Figure 1. Recirculating MUX Schematic
While this circuit is conceptually simple, it can be improved upon in several ways. Figure 2 shows
a functionally equivalent circuit using a gated clock. This circuit is higher performance because it
removes the MUX from the timing-critical data input to the flops. Removing these MUXes also
saves area. Finally, this circuit is lower power since the flops are not clocked in cycles they do not
need to be clocked.
NOTE: There are many possible ways of implementing gated clocking. However, most can be
generalized to the circuit in Figure 2.
Figure 2. Gated Clocking Schematic
The remainder of this paper uses this circuit as a basis for discussion, so a detailed explanation of
the logic is needed. In this circuit, the positive pulse of the clock signal is either enabled or
disabled by the gate signal. Thus, in any cycle when
GATE is deasserted low, GCLK will remain
low and no positive edge will be propagated to the downstream flip flops. The transparent-low
CLK
GATE
DQ
Q[MSB:LSB]
D[MSB:LSB]
0
1
DQ
GN
CLK
GCLK
GATE
GATE_PH2
DQ
Q[MSB:LSB]
D[MSB:LSB]
CLK
latch
CLK
nand
SNUG Boston 2002 3 Successful Gated Clocking
latch is used to hold the gate stable over the positive pulse of CLK in order to prevent clock
glitching. In order to be glitch free, there is a setup and a hold requirement at the NAND gate.
Figure 3. Clock Glitch Setup Check
Figure 3 shows the waveform for analyzing setup time checks. In this case, GATE changes late in
the cycle. The setup requirement occurs at the positive edge of the clock at the NAND gate,
CLK
nand
. The setup check analysis must use the following timing:
• The clock path starts at CLK and ends at the NAND gate. The timing must be for delays of the
positive edge of the clock.
• The data path starts before GATE, which is itself generated from flip-flops and logic clocked by
the positive edge of CLK, goes through the latch (D->Q), and ends at the NAND gate. The timing
must be for either positive edge or negative edge of GATE, whichever is longer.
Note that in this analysis, the latch is open and therefore, can be thought of as simply a delay
element in the path. Ideally, this path would not be analyzed as a latch path.
Figure 4. Clock Glitch Hold Check
Figure 4 shows the waveform for analyzing hold time checks. In this case, GATE changes early in
the cycle, during the positive pulse of the clock. Since
GATE_PH2 must be stable over the entire
CLK
GATE
GATE_PH2
GCLK
CLK
latch
CLK
nand
SETUP CHECK
CLK
GATE
GATE_PH2
GCLK
CLK
latch
CLK
nand
HOLD CHECK
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