366b_q_z00m_8dp_mobile_lpddr4x.pdf_LPDDR4FBGA366

lpddr4x

需积分: 5 77 浏览量更新于2023-03-03 评论 2 收藏 3.85MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源评论

资源推荐

Mobile LPDDR4X SDRAM

MT53D512M64D8

Features

• Ultra-low-voltage core and I/O power supplies

–V

DD1

= 1.70–1.95V; 1.80V nominal

–V

DD2

= 1.06–1.17V; 1.10V nominal

–V

DDQ

= 0.57–0.65V; 0.60V nominal

• Frequency range

– 1866–10 MHz (data rate range: 3733–20 Mb/s/

pin)

•16n prefetch DDR architecture

• 8 internal banks per channel for concurrent opera-

tion

• Single-data-rate CMD/ADR entry

• Bidirectional/differential data strobe per byte lane

• Programmable READ and WRITE latencies (RL/WL)

• Programmable and on-the-fly burst lengths (BL =

16, 32)

• Directed per-bank refresh for concurrent bank op-

eration and ease of command scheduling

• Up to 7.5 GB/s per die

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Selectable output drive strength (DS)

• Clock-stop capability

• RoHS-compliant, “green” packaging

• Programmable V

(ODT) termination

Options Marking

•V

DD1

DD2

DDQ

: 1.80V/1.10V/0.60V D

• Array configuration

– 512 Meg × 64 (4 channels × 16 I/O) 512M64

• Device configuration

– 256M16 × 8die in package D8

• FBGA “green” package

– 366-ball WFBGA (12.0mm × 12.7mm) HR

• Speed grade, cycle time

– 535ps @ RL = 32/36 -053

• Operating temperature range

– –30°C to +85°C WT

• Revision :B

Table 1: Key Timing Parameters

Speed

Grade

Clock Rate

(MHz)

Data Rate

(Mb/s/pin)

WRITE Latency READ Latency

Set A Set B DBI Disabled DBI Enabled

-053 1866 3733 16 30 32 36

Micron Confidential and Proprietary

366b: x64 Mobile LPDDR4X SDRAM

Features

CCMTD-554574167-10449

366b_q_z00m_8dp_mobile_lpddr4x.pdf – Rev. E 06/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Contents

General Description ....................................................................................................................................... 16

General Notes ............................................................................................................................................ 16

Package Block Diagrams ................................................................................................................................. 17

Ball Assignments and Descriptions ................................................................................................................. 18

Package Dimensions ....................................................................................................................................... 21

MR0, MR[6:5], MR8, MR13, MR24 Definition ................................................................................................... 22

Parameters ............................................................................................................................................... 23

Functional Description ................................................................................................................................... 25

Monolithic Device Addressing ......................................................................................................................... 25

Simplified Bus Interface State Diagram ............................................................................................................ 29

Power-Up and Initialization ............................................................................................................................ 30

Voltage Ramp ............................................................................................................................................. 31

Reset Initialization with Stable Power .......................................................................................................... 33

Power-Off Sequence ....................................................................................................................................... 34

Controlled Power-Off .................................................................................................................................. 34

Uncontrolled Power-Off .............................................................................................................................. 34

Mode Registers ............................................................................................................................................... 35

Mode Register Assignments and Definitions ................................................................................................ 35

Commands and Timing .................................................................................................................................. 61

Truth Tables ................................................................................................................................................... 61

ACTIVATE Command ..................................................................................................................................... 64

Read and Write Access Modes ......................................................................................................................... 65

Preamble and Postamble ................................................................................................................................ 65

Burst READ Operation .................................................................................................................................... 69

Read Timing ............................................................................................................................................... 71

LZ(DQS),

LZ(DQ),

HZ(DQS),

HZ(DQ) Calculation ..................................................................................... 71

LZ(DQS) and

HZ(DQS) Calculation for ATE (Automatic Test Equipment) .................................................... 72

LZ(DQ) and

HZ(DQ) Calculation for ATE (Automatic Test Equipment) ........................................................ 73

Burst WRITE Operation .................................................................................................................................. 75

Write Timing .............................................................................................................................................. 78

WPRE Calculation for ATE (Automatic Test Equipment) .............................................................................. 79

WPST Calculation for ATE (Automatic Test Equipment) ............................................................................... 79

MASK WRITE Operation ................................................................................................................................. 80

Mask Write Timing Constraints for BL16 ...................................................................................................... 82

Data Mask and Data Bus Inversion (DBI [DC]) Function ................................................................................... 84

WRITE and MASKED WRITE Operation DQS Control (WDQS Control) ............................................................. 88

WDQS Control Mode 1 – Read-Based Control .............................................................................................. 88

WDQS Control Mode 2 – WDQS_On/Off ...................................................................................................... 88

Preamble and Postamble Behavior .................................................................................................................. 92

Preamble, Postamble Behavior in READ-to-READ Operations ...................................................................... 92

READ-to-READ Operations – Seamless ........................................................................................................ 93

READ-to-READ Operations – Consecutive ................................................................................................... 94

WRITE-to-WRITE Operations – Seamless ................................................................................................... 101

WRITE-to-WRITE Operations – Consecutive ............................................................................................... 104

PRECHARGE Operation ................................................................................................................................. 108

Burst READ Operation Followed by Precharge ............................................................................................ 108

Burst WRITE Followed by Precharge ........................................................................................................... 109

Auto Precharge .............................................................................................................................................. 110

Burst READ With Auto Precharge ............................................................................................................... 110

Burst WRITE With Auto Precharge .............................................................................................................. 111

Micron Confidential and Proprietary

366b: x64 Mobile LPDDR4X SDRAM

Features

CCMTD-554574167-10449

366b_q_z00m_8dp_mobile_lpddr4x.pdf – Rev. E 06/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

RAS Lock Function .................................................................................................................................... 115

Delay Time From WRITE-to-READ with Auto Precharge .............................................................................. 116

REFRESH Command ..................................................................................................................................... 117

Burst READ Operation Followed by Per Bank Refresh .................................................................................. 123

Refresh Requirement ..................................................................................................................................... 124

SELF REFRESH Operation .............................................................................................................................. 125

Self Refresh Entry and Exit ......................................................................................................................... 125

Power-Down Entry and Exit During Self Refresh ......................................................................................... 126

Command Input Timing After Power-Down Exit ......................................................................................... 127

Self Refresh Abort ...................................................................................................................................... 128

MRR, MRW, MPC Commands During

XSR,

RFC ........................................................................................ 128

Power-Down Mode ........................................................................................................................................ 131

Power-Down Entry and Exit ....................................................................................................................... 131

Input Clock Stop and Frequency Change ........................................................................................................ 141

Clock Frequency Change – CKE LOW ......................................................................................................... 141

Clock Stop – CKE LOW ............................................................................................................................... 141

Clock Frequency Change – CKE HIGH ........................................................................................................ 141

Clock Stop – CKE HIGH ............................................................................................................................. 142

MODE REGISTER READ Operation ................................................................................................................ 143

MRR After a READ and WRITE Command .................................................................................................. 144

MRR After Power-Down Exit ...................................................................................................................... 146

MODE REGISTER WRITE ............................................................................................................................... 147

Mode Register Write States ......................................................................................................................... 148

REF

Current Generator (VRCG) ..................................................................................................................... 149

REF

Training ................................................................................................................................................. 151

REF(CA)

Training ........................................................................................................................................ 151

REF(DQ)

Training ....................................................................................................................................... 156

Command Bus Training ................................................................................................................................. 161

Command Bus Training Mode .................................................................................................................... 161

Training Sequence for Single-Rank Systems ................................................................................................ 162

Training Sequence for Multiple-Rank Systems ............................................................................................ 163

Relation Between CA Input Pin and DQ Output Pin ..................................................................................... 164

Write Leveling ............................................................................................................................................... 168

Mode Register Write-WR Leveling Mode ..................................................................................................... 168

Write Leveling Procedure ........................................................................................................................... 168

Input Clock Frequency Stop and Change .................................................................................................... 169

MULTIPURPOSE Operation ........................................................................................................................... 172

Read DQ Calibration Training ........................................................................................................................ 177

Read DQ Calibration Training Procedure .................................................................................................... 177

Read DQ Calibration Training Example ...................................................................................................... 179

MPC[READ DQ CALIBRATION] After Power-Down Exit ............................................................................... 180

Write Training ............................................................................................................................................... 180

Internal Interval Timer .............................................................................................................................. 186

DQS Interval Oscillator Matching Error ...................................................................................................... 188

OSC Count Readout Time .......................................................................................................................... 189

Thermal Offset .............................................................................................................................................. 191

Temperature Sensor ...................................................................................................................................... 191

ZQ Calibration ............................................................................................................................................... 192

ZQCAL Reset ............................................................................................................................................. 193

Multichannel Considerations ..................................................................................................................... 194

ZQ External Resistor, Tolerance, and Capacitive Loading ............................................................................. 195

Frequency Set Points ..................................................................................................................................... 196

Micron Confidential and Proprietary

366b: x64 Mobile LPDDR4X SDRAM

Features

CCMTD-554574167-10449

366b_q_z00m_8dp_mobile_lpddr4x.pdf – Rev. E 06/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.