16位高速数模转换芯片AD7705资料_fpga实现ad7705

AD7705

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REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

AD7705/AD7706

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1998

3 V/5 V, 1 mW

2-/3-Channel 16-Bit, Sigma-Delta ADCs

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AD7705: Two Fully Differential Input Channel ADCs

AD7706: Three Pseudo Differential Input Channel ADCs

16 Bits No Missing Codes

0.003% Nonlinearity

Programmable Gain Front End

Gains from 1 to 128

Three-Wire Serial Interface

SPI™, QSPI™, MICROWIRE™ and DSP Compatible

Schmitt Trigger Input on SCLK

Ability to Buffer the Analog Input

2.7 V to 3.3 V or 4.75 V to 5.25 V Operation

Power Dissipation 1 mW max @ 3␣ V

Standby Current 8 ␮A max

16-Lead DIP, 16-Lead SOIC and TSSOP Packages

GENERAL DESCRIPTION

The AD7705/AD7706 are complete analog front ends for low

frequency measurement applications. These two-/three-channel

devices can accept low level input signals directly from a trans-

ducer and produce a serial digital output. They employ a sigma-

delta conversion technique to realize up to 16 bits of no missing

codes performance. The selected input signal is applied to a

proprietary programmable gain front end based around an ana-

log modulator. The modulator output is processed by an on-

chip digital filter. The first notch of this digital filter can be

programmed via an on-chip control register allowing adjustment

of the filter cutoff and output update rate.

The AD7705/AD7706 operate from a single 2.7 V to 3.3 V or

4.75 V to 5.25 V supply. The AD7705 features two fully differ-

ential analog input channels while the AD7706 features three

pseudo differential input channels. Both devices feature a differ-

ential reference input. Input signal ranges of 0 mV to +20␣ mV

through 0 V to +2.5␣ V can be incorporated on both devices when

operating with a V

of 5 V and a reference of 2.5 V. They can

also handle bipolar input signal ranges of ±20␣ mV through ±2.5␣ V,

which are referenced to the AIN(–) inputs on the AD7705 and to

the COMMON input on the AD7706. The AD7705/AD7706,

with 3 V supply and a 1.225 V reference, can handle unipolar

input signal ranges of 0 mV to +10␣ mV through 0 V to +1.225␣ V.

Its bipolar input signal ranges are ±10␣ mV through ±1.225␣ V.

The AD7705/AD7706 thus perform all signal conditioning and

conversion for a two- or three-channel system.

The AD7705/AD7706 are ideal for use in smart, microcontroller

or DSP-based systems. They feature a serial interface that can

be configured for three-wire operation. Gain settings, signal

polarity and update rate selection can be configured in software

using the input serial port. The part contains self-calibration and

system calibration options to eliminate gain and offset errors on

the part itself or in the system.

CMOS construction ensures very low power dissipation, and the

power-down mode reduces the standby power consumption to

20␣ µW typ. These parts are available in a 16-lead, 0.3 inch-wide,

plastic dual-in-line package (DIP), a 16-lead wide body (0.3

inch) small outline (SOIC) package and also a low profile 16-

lead TSSOP.

PRODUCT HIGHLIGHTS

1. The AD7705/AD7706 consumes less than 1 mW at 3 V

supplies and 1␣ MHz master clock, making it ideal for use in

low power systems. Standby current is less than 8␣ µA.

2. The programmable gain input allows the AD7705/AD7706

to accept input signals directly from a strain gage or trans-

ducer, removing a considerable amount of signal conditioning.

3. The AD7705/AD7706 is ideal for microcontroller or DSP

processor applications with a three-wire serial interface re-

ducing the number of interconnect lines and reducing the

number of opto-couplers required in isolated systems.

4. The part features excellent static performance specifications

with 16 bits, no missing codes, ±0.003% accuracy and low

rms noise (<600␣ nV). Endpoint errors and the effects of

temperature drift are eliminated by on-chip calibration op-

tions, which remove zero-scale and full-scale errors.

*Protected by U.S. Patent Number 5,134,401.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor.

DD REF IN(–) REF IN(+)

AD7705/AD7706

MAX

PGA

BUFFER

CHARGE

BALANCING

A/D CONVERTER

S - D

MODULATOR

DIGITAL FILTER

A = 1<128

SERIAL INTERFACE

CLOCK

GENERATION

MCLK IN

MCLK OUT

GND

DRDY RESET

DIN

DOUT

SCLK

ANALOG

INPUT

CHANNELS

–2–

REV. A

AD7705/AD7706–SPECIFICATIONS

= +3 V or 5 V, REF IN(+) = +1.225␣ V with V

= 3 V and +2.5 V

with V

= 5 V; REF␣ IN(–) = GND; MCLK IN = 2.4576␣ MHz unless otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

Parameter B Version

Units Conditions/Comments

STATIC PERFORMANCE

No Missing Codes 16 Bits min Guaranteed by Design. Filter Notch < 60␣ Hz

Output Noise See Tables I and III Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity

±0.003 % of FSR max Filter Notch < 60␣ Hz. Typically ±0.0003%

Unipolar Offset Error See Note 3

Unipolar Offset Drift

0.5 µV/°C typ

Bipolar Zero Error See Note 3

Bipolar Zero Drift

0.5 µV/°C typ For Gains 1, 2 and 4

0.1 µV/°C typ For Gains 8, 16, 32, 64 and 128

Positive Full-Scale Error

See Note 3

Full-Scale Drift

4, 6

0.5 µV/°C typ

Gain Error

See Note 3

Gain Drift

4, 8

0.5 ppm of FSR/°C typ

Bipolar Negative Full-Scale Error

±0.003 % of FSR typ Typically ±0.001%

Bipolar Negative Full-Scale Drift

1 µV/°C typ For Gains of 1 to 4

0.6 µV/°C typ For Gains of 8 to 128

ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN Unless Noted

Input Common-Mode Rejection (CMR)

= 5 V

Gain = 1 96 dB typ

Gain = 2 105 dB typ

Gain = 4 110 dB typ

Gain = 8v128 130 dB typ

= 3 V

Gain = 1 105 dB typ

Gain = 2 110 dB typ

Gain = 4 120 dB typ

Gain = 8v128 130 dB typ

Normal-Mode 50 Hz Rejection

98 dB typ For Filter Notches of 25 Hz, 50 Hz, ±0.02 × f

NOTCH

Normal-Mode 60 Hz Rejection

98 dB typ For Filter Notches of 20 Hz, 60 Hz, ±0.02 × f

NOTCH

Common-Mode 50 Hz Rejection

150 dB typ For Filter Notches of 25 Hz, 50 Hz, ±0.02 × f

NOTCH

Common-Mode 60 Hz Rejection

150 dB typ For Filter Notches of 20 Hz, 60 Hz, ±0.02 × f

NOTCH

Absolute/Common-Mode REF IN Voltage

GND to V

V min to V max

Absolute/Common-Mode AIN Voltage

2, 9

GND – 30 mV V min BUF Bit of Setup Register = 0

+ 30␣ mV V max

Absolute/Common-Mode AIN Voltage

2, 9

GND + 50␣ mV V min BUF Bit of Setup Register = 1

– 1.5␣ V V max

AIN DC Input Current

1 nA max

AIN Sampling Capacitance

10 pF max

AIN Differential Voltage Range

0 to +V

REF

/GAIN

nom Unipolar Input Range (B/U Bit of Setup Register = 1)

±V

REF

/GAIN nom Bipolar Input Range (B/U Bit of Setup Register = 0)

AIN Input Sampling Rate, f

GAIN × f

CLKIN

/64 For Gains of 1 to 4

CLKIN

/8 For Gains of 8 to 128

Reference Input Range

REF IN(+) – REF IN(–) Voltage 1/1.75 V min/max V

= 2.7 V to 3.3 V. V

REF

= 1.225 ± 1% for Specified

Performance

REF IN(+) – REF IN(–) Voltage 1/3.5 V min/max V

= 4.75 V to 5.25 V. V

REF

= 2.5 ± 1% for Specified

Performance

REF IN Input Sampling Rate, f

CLKIN

/64

LOGIC INPUTS

Input Current

All Inputs Except MCLK IN ±1 µA max Typically ±20 nA

MCLK ±10 µA max Typically ±2 µA

All Inputs Except SCLK and MCLK IN

INL

, Input Low Voltage 0.8 V max V

= 5 V

0.4 V max V

= 3 V

INH

, Input High Voltage 2.0 V min V

= 3 V and 5 V

SCLK Only (Schmitt Triggered Input) V

= 5 V NOMINAL

T+

1.4/3 V min/V max

T–

0.8/1.4 V min/V max

T+

– V

T–

0.4/0.8 V min/V max

SCLK Only (Schmitt Triggered Input) V

= 3 V NOMINAL

T+

1/2.5 V min/V max

T–

0.4/1.1 V min/V max

T+

– V

T–

0.375/0.8 V min/V max

MCLK IN Only V

= 5 V NOMINAL

INL

, Input Low Voltage 0.8 V max

INH

, Input High Voltage 3.5 V min

MCLK IN Only V

= 3 V NOMINAL

INL

, Input Low Voltage 0.4 V max

INH

, Input High Voltage 2.5 V min

–3–REV. A

AD7705/AD7706

Parameter B Version

Units Conditions/Comments

LOGIC OUTPUTS (Including MCLK OUT)

, Output Low Voltage 0.4 V max I

SINK

= 800␣ µA Except for MCLK OUT.

= 5 V.

, Output Low Voltage 0.4 V max I

SINK

= 100␣ µA Except for MCLK OUT.

= 3 V.

, Output High Voltage 4 V min I

SOURCE

= 200 µA Except for MCLK OUT.

= 5 V.

, Output High Voltage V

–0.6 V min I

SOURCE

= 100␣ µA Except for MCLK OUT.

= 3 V.

Floating State Leakage Current ±10 µA max

Floating State Output Capacitance

9 pF typ

Data Output Coding Binary Unipolar Mode

Offset Binary Bipolar Mode

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit

(1.05 × V

REF

)/GAIN V max GAIN Is the Selected PGA Gain (1 to 128)

Negative Full-Scale Calibration Limit

–(1.05 × V

REF

)/GAIN V max GAIN Is the Selected PGA Gain (1 to 128)

Offset Calibration Limit

–(1.05 × V

REF

)/GAIN V max GAIN Is the Selected PGA Gain (1 to 128)

Input Span

(0.8 × V

REF

)/GAIN V min GAIN Is the Selected PGA Gain (1 to 128)

(2.1 × V

REF

)/GAIN V max GAIN Is the Selected PGA Gain (1 to 128)

POWER REQUIREMENTS

Voltage +2.7 to +3.3 V min to V max For Specified Performance

Power Supply Currents

Digital I/Ps = 0␣ V or V

. External MCLK IN and

CLK DIS = 1

0.32 mA max BUF Bit = 0. f

CLKIN

= 1␣ MHz. Gains of 1 to 128

0.6 mA max BUF Bit = 1. f

CLKIN

= 1␣ MHz. Gains of 1 to 128

0.4 mA max BUF Bit = 0. f

CLKIN

= 2.4576␣ MHz. Gains of 1 to 4

0.6 mA max BUF Bit = 0. f

CLKIN

= 2.4576␣ MHz. Gains of 8 to 128

0.7 mA max BUF Bit = 1. f

CLKIN

= 2.4576␣ MHz. Gains of 1 to 4

1.1 mA max BUF Bit = 1. f

CLKIN

= 2.4576␣ MHz. Gains of 8 to 128

Voltage +4.75 to +5.25 V min to V max For Specified Performance

Power Supply Currents

Digital I/Ps = 0␣ V or V

. External MCLK IN and

CLK DIS = 1.

0.45 mA max BUF Bit = 0. f

CLKIN

= 1␣ MHz. Gains of 1 to 128

0.7 mA max BUF Bit = 1. f

CLKIN

= 1␣ MHz. Gains of 1 to 128

0.6 mA max BUF Bit = 0. f

CLKIN

= 2.4576␣ MHz. Gains of 1 to 4

0.85 mA max BUF Bit = 0. f

CLKIN

= 2.4576␣ MHz. Gains of 8 to 128

0.9 mA max BUF Bit = 1. f

CLKIN

= 2.4576␣ MHz. Gains of 1 to 4

1.3 mA max BUF Bit = 1. f

CLKIN

= 2.4576␣ MHz. Gains of 8 to 128

Standby (Power-Down) Current

16 µA max External MCLK IN = 0 V or V

. V

= 5 V. See Figure 9

8 µA max External MCLK IN = 0 V or V

. V

= 3 V

Power Supply Rejection

See Note 19 dB typ

NOTES

Temperature range as follows: B Version, –40°C to +85°C.

These numbers are established from characterization or design at initial product release.

A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I and III. This applies after calibration at the

temperature of interest.

Recalibration at any temperature will remove these drift errors.

Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.

Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.

Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for

bipolar ranges.

Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed.

This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than V

+ 30 mV or go more negative than

GND – 30␣ mV. Parts are functional with voltages down to GND – 200 mV, but with increased leakage at high temperature.

The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–) on the AD7705 and is given with respect to the COMMON input on the

AD7706. The absolute voltage on the analog inputs should not go more positive than V

+ 30␣ mV, or go more negative than GND␣ – 30␣ mV for specified performance, input

voltages of GND – 200 mV can be accommodated, but with increased leakage at high temperature.

REF

= REF IN(+) – REF IN(–).

These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.

Sample tested at +25°C to ensure compliance.

After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s.

These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed V

+ 30␣ mV or go more negative than GND – 30␣ mV. The offset

calibration limit applies to both the unipolar zero point and the bipolar zero point.

When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the V

current and power dissipation will vary depending on the crystal or

resonator type (see Clocking and Oscillator Circuit section).

If the external master clock continues to run in standby mode, the standby current increases to 150␣ µA typical at 5 V and 75 µA at 3 V. When using a crystal or ceramic

resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal

or resonator type (see Standby Mode section).

Measured at dc and applies in the selected passband. PSRR at 50␣ Hz will exceed 120␣ dB with filter notches of 25 Hz or 50␣ Hz. PSRR at 60␣ Hz will exceed 120␣ dB with filter

notches of 20 Hz or 60␣ Hz.

depends on both gain and V

Gain 1 2 4 8–128

= 3 V 86 78 85 93

= 5 V 90 78 84 91

Specifications subject to change without notice.

AD7705/AD7706

–4–

REV. A

TIMING CHARACTERISTICS

1, 2

Limit at T

MIN

, T

MAX

Parameter (B Version) Units Conditions/Comments

CLKIN

3, 4

400 kHz min Master Clock Frequency: Crystal Oscillator or Externally Supplied

2.5 MHz max for Specified Performance

CLKIN LO

0.4 × t

CLKIN

ns min Master Clock Input Low Time. t

CLKIN

= 1/f

CLKIN

CLKIN HI

0.4 × t

CLKIN

ns min Master Clock Input High Time

500 × t

CLKIN

ns nom DRDY High Time

100 ns min RESET Pulsewidth

Read Operation

0 ns min DRDY to CS Setup Time

120 ns min CS Falling Edge to SCLK Rising Edge Setup Time

0 ns min SCLK Falling Edge to Data Valid Delay

80 ns max V

= +5␣ V

100 ns max V

= +3.0␣ V

100 ns min SCLK High Pulsewidth

100 ns min SCLK Low Pulsewidth

0 ns min CS Rising Edge to SCLK Rising Edge Hold Time

10 ns min Bus Relinquish Time after SCLK Rising Edge

60 ns max V

= +5␣ V

100 ns max V

= +3.0␣ V

100 ns max SCLK Falling Edge to DRDY High

Write Operation

120 ns min CS Falling Edge to SCLK Rising Edge Setup Time

30 ns min Data Valid to SCLK Rising Edge Setup Time

20 ns min Data Valid to SCLK Rising Edge Hold Time

100 ns min SCLK High Pulsewidth

100 ns min SCLK Low Pulsewidth

0 ns min CS Rising Edge to SCLK Rising Edge Hold Time

NOTES

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

) and timed from a voltage level of 1.6 V.

See Figures 16 and 17.

CLKIN

Duty Cycle range is 45% to 55%. f

CLKIN

must be supplied whenever the AD7705/AD7706 is not in Standby mode. If no clock is present in this case, the device

can draw higher current than specified and possibly become uncalibrated.

The AD7705/AD7706 is production tested with f

CLKIN

at 2.4576␣ MHz (1␣ MHz for some I

tests). It is guaranteed by characterization to operate at 400␣ kHz.

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V

or V

limits.

These numbers are derived from the measured time taken by the data output to change 0.5␣ V when loaded with the circuit of Figure 1. The measured number is

then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and as such are independent of external bus loading capacitances.

DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care

should be taken that subsequent reads do not occur close to the next output update.

TO OUTPUT

50pF

SINK

(800mA AT V

= +5V

100mA AT V

= +3V)

+1.6V

SOURCE

(200mA AT V

= +5V

100mA AT V

= +3V)

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

= +2.7␣ V to +5.25␣ V; GND = 0 V; f

CLKIN

= 2.4576␣ MHz; Input Logic 0 = 0 V, Logic 1 = V

unless otherwise noted.)

AD7705/AD7706

–5–REV. A

ABSOLUTE MAXIMUM RATINGS*

= +25°C unless otherwise noted)

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V

Analog Input Voltage to GND . . . . . . . .–0.3 V to V

+ 0.3␣ V

Reference Input Voltage to GND . . . . .–0.3 V to V

+ 0.3␣ V

Digital Input Voltage to GND . . . . . . . . –0.3 V to V

+ 0.3 V

Digital Output Voltage to GND . . . . . .–0.3 V to V

+ 0.3 V

Operating Temperature Range

Commercial (B Version) . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

Lead Temperature, (Soldering, 10 sec) . . . . . . . . . .+260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 139°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C

␣␣␣␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000␣ V

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Supply Range Description Options

AD7705BN 2.7 V to 5.25 V –40°C to +85°C Plastic DIP N-16

AD7705BR 2.7 V to 5.25 V –40°C to +85°C SOIC R-16

AD7705BRU 2.7 V to 5.25 V –40°C to +85°C TSSOP RU-16

EVAL-AD7705EB Evaluation Board

AD7706BN 2.7 V to 5.25 V –40°C to +85°C Plastic DIP N-16

AD7706BR 2.7 V to 5.25 V –40°C to +85°C SOIC R-16

AD7706BRU 2.7 V to 5.25 V –40°C to +85°C TSSOP RU-16

EVAL-AD7706EB Evaluation Board

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