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W25M02GVZEIG.pdf
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The W25M02GV (2 x 1G-bit) Serial MCP (Multi Chip Package) Flash memory is based on the W25N Serial SLC NAND SpiFlash® series by stacking two individual W25N01GV die into a standard 8-pin package. It offers the highest memory density for the low pin-count package, as well as Concurrent Operations in Serial Flash memory for the first time. The W25M SpiStack® series is ideal for small form factor system designs, and applications that demand high Program/Erase data throughput. All W25N SpiFlash family devices are offered in space-saving packages which were impossible to use in the past for the typical NAND flash memory.
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W25M02GV
Publication Release Date: May 09, 2018
Revision F
Featuring
3V 2G-BIT (2 x 1G-BIT)
SERIAL SLC NAND FLASH MEMORY WITH
DUAL/QUAD SPI
BUFFER READ & CONTINUOUS READ
CONCURRENT OPERATIONS
W25M02GV
- 1 -
Table of Contents
1. GENERAL DESCRIPTIONS ............................................................................................................. 6
2. FEATURES ....................................................................................................................................... 6
3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7
3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 7
3.2 Pad Description WSON 8x6-mm .......................................................................................... 7
3.3 Pin Configuration SOIC 300-mil ........................................................................................... 8
3.4 Pin Description SOIC 300-mil ............................................................................................... 8
3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 9
3.6 Ball Description TFBGA 8x6-mm ......................................................................................... 9
4. PIN DESCRIPTIONS ...................................................................................................................... 10
4.1 Serial MCP (SpiStack
®
) Device Configuration ................................................................... 10
4.2 Chip Select (/CS) ................................................................................................................ 10
4.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................. 10
4.4 Write Protect (/WP) ............................................................................................................. 11
4.5 HOLD (/HOLD) ................................................................................................................... 11
4.6 Serial Clock (CLK) .............................................................................................................. 11
5. SINGLE DIE (W25N01GV) BLOCK DIAGRAM .............................................................................. 12
6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 13
6.1 Device Operation Flow ....................................................................................................... 13
6.1.1 Stacked Die Operations ........................................................................................................ 13
6.1.2 Standard SPI Instructions ..................................................................................................... 13
6.1.3 Dual SPI Instructions ............................................................................................................ 14
6.1.4 Quad SPI Instructions ........................................................................................................... 14
6.1.5 Hold Function ........................................................................................................................ 14
6.2 Write Protection .................................................................................................................. 15
7. PROTECTION, CONFIGURATION AND STATUS REGISTERS .................................................. 16
7.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ......................... 16
7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable .................. 16
7.1.2 Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable ................................. 17
7.1.3 Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable ..................... 17
7.2 Configuration Register / Status Register-2 (Volatile Writable) ........................................... 18
7.2.1 One Time Program Lock Bit (OTP-L) – OTP lockable .......................................................... 18
7.2.2 Enter OTP Access Mode Bit (OTP-E) – Volatile Writable ..................................................... 18
7.2.3 Status Register-1 Lock Bit (SR1-L) – OTP lockable ............................................................. 18
7.2.4 ECC Enable Bit (ECC-E) – Volatile Writable ......................................................................... 19
7.2.5 Buffer Read / Continuous Read Mode Bit (BUF) – Volatile Writable ..................................... 19
7.3 Status Register-3 (Status Only) .......................................................................................... 20
7.3.1 Look-Up Table Full (LUT-F) – Status Only............................................................................ 20
W25M02GV
Publication Release Date: May 09, 2018
- 2 - Revision F
7.3.2 Cumulative ECC Status (ECC-1, ECC-0) – Status Only ....................................................... 20
7.3.3 Program/Erase Failure (P-FAIL, E-FAIL) – Status Only ........................................................ 21
7.3.4 Write Enable Latch (WEL) – Status Only .............................................................................. 21
7.3.5 Erase/Program In Progress (BUSY) – Status Only ............................................................... 21
7.3.6 Reserved Bits – Non Functional ........................................................................................... 21
7.4 Single Die W25N01GV Status Register Memory Protection .............................................. 22
8. INSTRUCTIONS ............................................................................................................................. 23
8.1 Device ID and Instruction Set Tables ................................................................................. 23
8.1.1 Manufacturer and Device Identification ................................................................................. 23
8.1.2 Instruction Set Table 1 (Continuous Read, BUF = 0, xxIT Default Power Up Mode)
(11)
........ 24
8.1.3 Instruction Set Table 2 (Buffer Read, BUF = 1, xxIG Default Power Up Mode)
(12)
................ 25
8.2 Instruction Descriptions ...................................................................................................... 27
8.2.1 Software Die Select (C2h) .................................................................................................... 27
8.2.2 Device Reset (FFh) ............................................................................................................... 28
8.2.3 Read JEDEC ID (9Fh) .......................................................................................................... 29
8.2.4 Read Status Register (0Fh / 05h) ......................................................................................... 30
8.2.5 Write Status Register (1Fh / 01h) ......................................................................................... 31
8.2.6 Write Enable (06h) ................................................................................................................ 32
8.2.7 Write Disable (04h) ............................................................................................................... 32
8.2.8 Bad Block Management (A1h) .............................................................................................. 33
8.2.9 Read BBM Look Up Table (A5h) .......................................................................................... 34
8.2.10 Last ECC Failure Page Address (A9h) ............................................................................... 35
8.2.11 128KB Block Erase (D8h) ................................................................................................... 36
8.2.12 Load Program Data (02h) / Random Load Program Data (84h) ......................................... 37
8.2.13 Quad Load Program Data (32h) / Quad Random Load Program Data (34h) ...................... 38
8.2.14 Program Execute (10h) ....................................................................................................... 39
8.2.15 Page Data Read (13h) ........................................................................................................ 40
8.2.16 Read Data (03h) ................................................................................................................. 41
8.2.17 Fast Read (0Bh) ................................................................................................................. 42
8.2.18 Fast Read with 4-Byte Address (0Ch) ................................................................................. 43
8.2.19 Fast Read Dual Output (3Bh) ............................................................................................. 44
8.2.20 Fast Read Dual Output with 4-Byte Address (3Ch)............................................................. 45
8.2.21 Fast Read Quad Output (6Bh) ............................................................................................ 46
8.2.22 Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 47
8.2.23 Fast Read Dual I/O (BBh) ................................................................................................... 48
8.2.24 Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 49
8.2.25 Fast Read Quad I/O (EBh) ................................................................................................. 50
8.2.26 Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................. 52
8.2.27 Accessing Unique ID / Parameter / OTP Pages (OTP-E=1) ............................................... 54
8.2.28 Parameter Page Data Definitions ....................................................................................... 55
9. ELECTRICAL CHARACTERISTICS
(1)
............................................................................................ 56
W25M02GV
- 3 -
9.1
Absolute Maximum Ratings
(2)
............................................................................................. 56
9.2 Operating Ranges .............................................................................................................. 56
9.3 Power-up Power-down Timing Requirements .................................................................... 57
9.4 DC Electrical Characteristics .............................................................................................. 58
9.5 AC Measurement Conditions ............................................................................................. 59
9.6 AC Electrical Characteristics
(3)
........................................................................................... 60
9.7 Serial Output Timing ........................................................................................................... 62
9.8 Serial Input Timing .............................................................................................................. 62
9.9 /HOLD Timing ..................................................................................................................... 62
9.10 /WP Timing ......................................................................................................................... 62
10. INVALID BLOCK MANAGEMENT .................................................................................................. 63
10.1 Invalid blocks ...................................................................................................................... 63
10.2 Initial invalid blocks ............................................................................................................. 63
11. PACKAGE SPECIFICATIONS ....................................................................................................... 64
11.1 8-Pad WSON 8x6-mm (Package Code ZE) ....................................................................... 64
11.2 16-Pin SOIC 300-mil (Package Code SF) .......................................................................... 65
11.3 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 Ball Array) ......................................... 66
11.4 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 Ball Array) ............................................ 67
12. ORDERING INFORMATION .......................................................................................................... 68
12.1 Valid Part Numbers and Top Side Marking ........................................................................ 69
13. REVISION HISTORY ...................................................................................................................... 70
W25M02GV
Publication Release Date: May 09, 2018
- 4 - Revision F
Table of Figures
Figure 1a. W25M02GV Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE) ............................. 7
Figure 1b. W25M02GV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) ................................. 8
Figure 1c. W25M02GV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC) .................. 9
Figure 2a. W25M02GV Device Configuration ............................................................................................. 10
Figure 2b. Single Die W25N01GV Flash Memory Architecture and Addressing ....................................... 12
Figure 2c. W25M02GV Flash Memory Operation Diagram ........................................................................ 13
Figure 3a. Protection Register / Status Register-1 (Address Axh) ............................................................. 16
Figure 3b. Configuration Register / Status Register-2 (Address Bxh) ........................................................ 18
Figure 3c. Status Register-3 (Address Cxh) ............................................................................................... 20
Figure 4. Software Die Select Instruction ................................................................................................... 27
Figure 5. Device Reset Instruction .............................................................................................................. 28
Figure 6. Read JEDEC ID Instruction ......................................................................................................... 29
Figure 7. Read Status Register Instruction ................................................................................................. 30
Figure 8. Write Status Register-1/2/3 Instruction ........................................................................................ 31
Figure 9. Write Enable Instruction ............................................................................................................... 32
Figure 10. Write Disable Instruction ............................................................................................................ 32
Figure 11. Bad Block Management Instruction ........................................................................................... 33
Figure 12. Read BBM Look Up Table Instruction ....................................................................................... 34
Figure 13. Last ECC Failure Page Address Instruction .............................................................................. 35
Figure 14. 128KB Block Erase Instruction .................................................................................................. 36
Figure 15. Load / Random Load Program Data Instruction ........................................................................ 37
Figure 16. Quad Load / Quad Random Load Program Data Instruction .................................................... 38
Figure 17. Program Execute Instruction ..................................................................................................... 39
Figure 18. Page Data Read Instruction ...................................................................................................... 40
Figure 19a. Read Data Instruction (Buffer Read Mode, BUF=1) ................................................................ 41
Figure 19b. Read Data Instruction (Continuous Read Mode, BUF=0) ....................................................... 41
Figure 20a. Fast Read Instruction (Buffer Read Mode, BUF=1) ................................................................ 42
Figure 20b. Fast Read Instruction (Continuous Read Mode, BUF=0)........................................................ 42
Figure 21a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ............................... 43
Figure 21b. Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ...................... 43
Figure 22a. Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1) ............................................ 44
Figure 22b. Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0) ................................... 44
Figure 23a. Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ........... 45
Figure 23b. Fast Read Dual Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) .. 45
Figure 24a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1) .......................................... 46
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