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i.MX 6UltraLite Applications
Processor Reference Manual
Document Number: IMX6ULRM
Rev. 2, 03/2017
i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Introduction
1.1 About This Document...................................................................................................................................................139
1.1.1 Audience.................................................................................................................................................... 139
1.1.2 Organization...............................................................................................................................................139
1.1.3 Suggested Reading.....................................................................................................................................140
1.1.3.1 General Information...............................................................................................................140
1.1.3.2 Related Documentation..........................................................................................................140
1.1.4 Conventions............................................................................................................................................... 140
1.1.5 Register Access..........................................................................................................................................142
1.1.5.1 Register Diagram Field Access Type Legend........................................................................142
1.1.5.2 Register Macro Usage............................................................................................................143
1.1.6 Signal Conventions.................................................................................................................................... 144
1.1.7 Acronyms and Abbreviations.....................................................................................................................144
1.2 Introduction...................................................................................................................................................................147
1.3 Target Applications.......................................................................................................................................................147
1.4 Features.........................................................................................................................................................................147
1.5 Architectural Overview.................................................................................................................................................151
1.5.1 Simplified Block Diagram......................................................................................................................... 151
1.5.2 Architectural Partitioning...........................................................................................................................152
1.5.3 Endianness Support....................................................................................................................................154
1.5.4 Memory Interfaces..................................................................................................................................... 154
Chapter 2
Memory Maps
2.1 Memory system overview.............................................................................................................................................155
2.2 ARM Platform Memory Map....................................................................................................................................... 155
2.3 DMA memory map.......................................................................................................................................................160
Chapter 3
i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017
NXP Semiconductors 3
Section number Title Page
Interrupts and DMA Events
3.1 Overview.......................................................................................................................................................................163
3.2 Cortex A7 interrupts..................................................................................................................................................... 163
3.3 SDMA event mapping.................................................................................................................................................. 167
Chapter 4
External Signals and Pin Multiplexing
4.1 Overview.......................................................................................................................................................................169
4.1.1 Muxing Options......................................................................................................................................... 169
Chapter 5
Fusemap
5.1 Boot Fusemap............................................................................................................................................................... 193
5.2 Lock Fusemap...............................................................................................................................................................204
5.3 Fusemap Descriptions Table.........................................................................................................................................205
Chapter 6
External Memory Controllers
6.1 Overview.......................................................................................................................................................................215
6.2 Multi-mode DDR controller (MMDC) overview and feature summary...................................................................... 215
6.3 EIM-PSRAM/NOR flash controller overview..............................................................................................................216
6.3.1 EIM features...............................................................................................................................................216
6.3.2 EIM boot scenarios.................................................................................................................................... 217
6.3.3 EIM boot configuration..............................................................................................................................217
6.3.4 OneNAND requirements............................................................................................................................218
Chapter 7
System Debug
7.1 Overview.......................................................................................................................................................................219
7.2 Chip and ARM Platform Debug Architecture.............................................................................................................. 219
7.2.1 Debug Features.......................................................................................................................................... 220
7.2.2 Debug system components.........................................................................................................................220
7.2.2.1 AMBA Trace Bus (ATB).......................................................................................................221
7.2.2.2 ATB replicator....................................................................................................................... 221
i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017
4 NXP Semiconductors
Section number Title Page
7.2.2.3 Embedded Cross Triggering.................................................................................................. 221
7.2.2.3.1 Cross-Trigger Matrix (CTM)..........................................................................222
7.2.2.3.2 Cross-Trigger Interface (CTI).........................................................................223
7.2.2.4 Debug Access Port (DAP)..................................................................................................... 223
7.2.3 Chip-Specific SJC Features....................................................................................................................... 224
7.2.3.1 JTAG Disable Mode.............................................................................................................. 224
7.2.3.2 JTAG ID.................................................................................................................................224
7.2.4 System JTAG Controller - SJC..................................................................................................................224
7.2.5 System JTAG controller main features......................................................................................................225
7.2.6 SJC TAP Port.............................................................................................................................................225
7.2.7 SJC main blocks.........................................................................................................................................225
7.3 Smart DMA (SDMA) core............................................................................................................................................226
7.3.1 SDMA On Chip Emulation Module (OnCE) Feature Summary............................................................... 226
7.3.1.1 Other SDMA Debug Functionality........................................................................................227
7.3.1.2 SDMA ROM Patching...........................................................................................................228
7.4 Miscellaneous............................................................................................................................................................... 228
7.4.1 Clock/Reset/Power.....................................................................................................................................228
7.5 Supported tools............................................................................................................................................................. 228
Chapter 8
System Boot
8.1 Overview.......................................................................................................................................................................231
8.2 Boot modes................................................................................................................................................................... 232
8.2.1 Boot mode pin settings...............................................................................................................................233
8.2.2 High-level boot sequence...........................................................................................................................233
8.2.3 Boot From Fuses mode (BOOT_MODE[1:0] = 00b)................................................................................234
8.2.4 Serial Downloader......................................................................................................................................235
8.2.5 Internal Boot mode (BOOT_MODE[1:0] = 0b10).................................................................................... 237
8.2.6 Boot security settings.................................................................................................................................237
8.3 Device configuration.....................................................................................................................................................238
i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017
NXP Semiconductors 5
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