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SD Host Controller Standard Specification Version 1.0 © Copyright SD Association, 2002-2003
1
SD Host Controller
Standard Specification
Draft Version 1.0
June, 2003
Technical Committee SDA
SDA Confidential
SD Host Controller Standard Specification Version 1.0 © Copyright SD Association, 2002-2003
2
Revision History
Date Version Changes compared to previous issue
Jun. 13, 2003 1.0 Base version initial release
Publisher and Copyright Holder:
SD Association
719 San Benito St., Suite C
Hollister, CA 95023
USA
Phone: +1 831 636 7322
Fax: +1 831 623 2248
E-mail: president@sdcard.org
Confidentiality:
This document shall be treated as confidential under the Non Disclosure Agreement (NDA), which has been
signed by the obtainer. Reproduction in whole or in part is prohibited without prior written permission of SD
Association
Exemption:
None will be liable for any damages from use of this document.
SDA Confidential
SD Host Controller Standard Specification Version 1.0 © Copyright SD Association, 2002-2003
3
Table of Contents
1.
General............................................................................................................................................................ 6
1.1 Related Documents ................................................................................................................................. 6
1.2 Conventions Used in This Document .....................................................................................................6
1.2.1 Naming Conventions ......................................................................................................................... 6
1.2.2 Numbers and Number Bases............................................................................................................. 6
1.2.3 Key Words ......................................................................................................................................... 6
1.2.4 Special Terms .................................................................................................................................... 7
1.2.5 Implementation Notes........................................................................................................................ 7
2.
Overview of the SD Standard Host................................................................................................................ 8
2.1 Scope of the Standard SD Host............................................................................................................... 8
2.2
Register Map ........................................................................................................................................... 9
2.3 Multiple Slot support ..............................................................................................................................9
2.4 Supporting DMA ................................................................................................................................... 10
2.5 SD Command generation ...................................................................................................................... 10
2.6 Suspend and Resume mechanism ........................................................................................................ 11
2.7 Buffer Control........................................................................................................................................ 12
2.7.1 Policy of the Host Buffer Access .................................................................................................... 12
2.7.2 Determining Buffer block length................................................................................................... 13
2.7.3 Dividing large data transfer .......................................................................................................... 13
2.7.4 Data lengths which cannot be divided by block size..................................................................... 13
2.8 Relationship between Interrupt Control Registers ............................................................................. 14
2.9 HW Block Diagram and timing part .................................................................................................... 16
2.10 Power state definition of SD Host Controller ...................................................................................... 17
2.11 Auto CMD12 .......................................................................................................................................... 18
3.
SD Host Standard Register.......................................................................................................................... 19
3.1 Summary of register set........................................................................................................................ 19
3.1.1 SD Host Control Register Map ...................................................................................................... 19
3.1.2 Configuration Register Types ........................................................................................................ 19
3.1.3 Register Initial values.................................................................................................................... 20
3.1.4 Reserved bits of register................................................................................................................. 20
3.2 SD Host Standard Register................................................................................................................... 21
3.2.1 System Address Register (Offset 000h).......................................................................................... 21
3.2.2 Block Size Register (Offset 004h).................................................................................................... 22
3.2.3 Block Count Register (Offset 006h) ................................................................................................. 23
3.2.4 Argument Register (Offset 008h) ..................................................................................................... 24
3.2.5 Transfer Mode Register (Offset 00Ch)............................................................................................. 25
3.2.6 Command Register (Offset 00Eh).................................................................................................... 27
3.2.7 Response Register (Offset 010h) .................................................................................................... 29
3.2.8 Buffer Data Port Register (Offset 020h) ........................................................................................... 30
3.2.9 Present State Register (Offset 024h)............................................................................................... 31
3.2.10 Host Control Register (Offset 028h)................................................................................................. 37
3.2.11 Power Control Register (Offset 029h)............................................................................................. 38
3.2.12 Block Gap Control Register (Offset 02Ah) ....................................................................................... 39
3.2.13 Wakeup Control Register (Offset 02Bh)........................................................................................... 41
3.2.14 Clock Control Register (Offset 02Ch)............................................................................................... 42
SDA Confidential
SD Host Controller Standard Specification Version 1.0 © Copyright SD Association, 2002-2003
4
3.2.15 Timeout Control Register (Offset 02Eh)........................................................................................... 44
3.2.16 Software Reset Register (Offset 02Fh)............................................................................................ 45
3.2.17 Normal Interrupt Status Register (Offset 030h)................................................................................ 47
3.2.18 Error Interrupt Status Register (Offset 032h) ................................................................................... 50
3.2.19 Normal Interrupt Status Enable Register (Offset 034h).................................................................... 52
3.2.20 Error Interrupt Status Enable Register (Offset 036h) ....................................................................... 54
3.2.21 Normal Interrupt Signal Enable Register (Offset 038h).................................................................... 56
3.2.22 Error Interrupt Signal Enable Register (Offset 03Ah)....................................................................... 58
3.2.23 Auto CMD12 Error Status Register (Offset 03Ch) ........................................................................... 60
3.2.24 Capabilities Register (Offset 040h) ................................................................................................. 62
3.2.25 Maximum Current Capabilities Register (Offset 048h)..................................................................... 64
3.2.26 Slot Interrupt Status Register (Offset 0FCh) .................................................................................... 65
3.2.27 Host Controller Version Register (Offset 0FEh) ............................................................................... 66
4.
SEQUENCE.................................................................................................................................................. 67
4.1 SD Card Detection................................................................................................................................. 67
4.2 SD Clock Control ................................................................................................................................... 68
4.2.1 SD Clock Supply Sequence ............................................................................................................ 68
4.2.2 SD Clock Stop Sequence ................................................................................................................ 69
4.2.3 SD Clock Frequency Change Sequence......................................................................................... 69
4.3 SD Bus Power Control........................................................................................................................... 70
4.4 Changing Bus Width ............................................................................................................................. 72
4.5 Timeout Setting on DAT Line............................................................................................................... 73
4.6 SD Transaction Generation .................................................................................................................. 73
4.6.1 Transaction Control without Data Transfer Using DAT Line...................................................... 74
4.6.1.1 The sequence for issue of the SD Command.......................................................................... 74
4.6.1.2 The sequence for complete command ..................................................................................... 76
4.6.2 Transaction Control with Data Transfer Using DAT Line ........................................................... 77
4.6.2.1 Not using DMA........................................................................................................................ 78
4.6.2.2 Using DMA.............................................................................................................................. 80
4.7 Abort Transaction.................................................................................................................................. 82
4.7.1 Asynchronous Abort ....................................................................................................................... 82
4.7.2 Synchronous Abort ......................................................................................................................... 83
4.8 Error Recovery....................................................................................................................................... 84
4.8.1 Error Interrupt Recovery............................................................................................................... 86
4.8.2 Auto CMD12 Error Recovery......................................................................................................... 89
4.9 Wakeup Control (Optional) ................................................................................................................... 92
4.10 Suspend/Resume (Optional).................................................................................................................. 94
4.10.1 Suspend Sequence.......................................................................................................................... 94
4.10.2 Resume Sequence........................................................................................................................... 96
4.10.3 Read transaction wait / continue timing....................................................................................... 97
4.10.4 Write transaction wait / continue timing ...................................................................................... 99
A.1
PCI configuration register ...................................................................................................................... 101
A.1.1
Register Map ....................................................................................................................................... 101
A.1.2
SD Controller Configuration Register MAP....................................................................................... 102
A.1.3
PCI Configuration Register ................................................................................................................ 103
A.1.3.1 Class Code Register (Offset 09h).............................................................................................. 103
A.1.3.2 Base Address Register (Offset 10h).......................................................................................... 104
A.1.3.3 Slot Information Register (Offset 40h) .................................................................................... 105
A.1.4
The relation between Device State, Power and Clock ....................................................................... 106
SDA Confidential
SD Host Controller Standard Specification Version 1.0 © Copyright SD Association, 2002-2003
5
A.1.5
Generate PME interrupt by the Wakeup Events............................................................................... 106
A.2
Abbreviations and terms ........................................................................................................................ 107
SDA Confidential
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