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4th-Order
DS
Modulator
Programmable
DigitalFilter
SPI
Interface
Calibration
Control
CLK
AVDD
AVSS
DVDD
DGND
Over-Range
ModulatorOutput
ADS1282
DOUT
DIN
DRDY
SCLK
SYNC
RESET
PWDN
3
PGA
MUX
Input1
Input2
VREFN VREFP
V
COM
ADS1282
www.ti.com
SBAS418G –SEPTEMBER 2007–REVISED MAY 2010
High-Resolution Analog-to-Digital Converter
Check for Samples: ADS1282
1
FEATURES
DESCRIPTION
2
• High Resolution:
The ADS1282 is an extremely high-performance,
130dB SNR (250SPS, High-Resolution Mode)
single-chip analog-to-digital converter (ADC) with an
127dB SNR (250SPS, Low-Power Mode)
integrated, low-noise programmable gain amplifier
(PGA) and two-channel input multiplexer (MUX). The
• High Accuracy:
ADS1282 is suitable for the demanding needs of
THD: –122dB
energy exploration and seismic monitoring
INL: 0.5ppm
environments.
• Low-Noise PGA
The converter uses a fourth-order, inherently stable,
• Two-Channel Input MUX
delta-sigma (ΔΣ) modulator that provides outstanding
• Inherently-Stable Modulator with Fast
noise and linearity performance. The modulator is
Responding Over-Range Detection
used either in conjunction with the on-chip digital
filter, or can be bypassed for use with post
• Flexible Digital Filter:
processing filters.
Sinc + FIR + IIR (Selectable)
Linear or Minimum Phase Response
The flexible input MUX provides an additional
Programmable High-Pass Filter
external input for measurement, as well as internal
self-test connections. The PGA features outstanding
Selectable FIR Data Rates: 250SPS to 4kSPS
low noise (5nV/√Hz) and high input impedance,
• Filter Bypass Option
allowing easy interfacing to geophones and
• Low Power Consumption:
hydrophones over a wide range of gains.
High-Resolution Mode: 25mW
The digital filter provides selectable data rates from
Low-Power Mode: 17mW
250 to 4000 samples per second (SPS). The
Shutdown: 10mW
high-pass filter (HPF) features an adjustable corner
• Offset and Gain Calibration Engine
frequency. On-chip gain and offset scaling registers
• SYNC Input support system calibration.
• Analog Supply:
The synchronization input (SYNC) can be used to
Unipolar (+5V) or Bipolar (±2.5V)
synchronize the conversions of multiple ADS1282s.
The SYNC input also accepts a clock input for
• Digital Supply: 1.8V to 3.3V
continuous alignment of conversions from an external
source.
APPLICATIONS
Two operating modes allow optimization of noise and
• Energy Exploration
power. Together, the amplifier, modulator, and filter
• Seismic Monitoring
dissipate 25mW and only 17mW in low-power mode.
• High-Accuracy Instrumentation
The ADS1282 is available in a compact TSSOP-28
package and is fully specified from –40°C to +85°C,
with a maximum operating range to +125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS1282
SBAS418G –SEPTEMBER 2007–REVISED MAY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range (unless otherwise noted).
ADS1282 UNIT
AVDD to AVSS –0.3 to +5.5 V
AVSS to DGND –2.8 to +0.3 V
DVDD to DGND –0.3 to +3.9 V
Input current 100, momentary mA
Input current 10, continuous mA
Analog input voltage AVSS – 0.3 to AVDD + 0.3 V
Digital input voltage to DGND –0.3 to DVDD + 0.3 V
Maximum junction temperature +150 °C
Operating temperature range –40 to +125 °C
Storage temperature range –60 to +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1282
ADS1282
www.ti.com
SBAS418G –SEPTEMBER 2007–REVISED MAY 2010
ELECTRICAL CHARACTERISTICS
Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, f
CLK
(1)
= 4.096MHz, VREFP = +2.5V,
VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, High-Resolution Mode, and f
DATA
= 1000SPS, unless otherwise noted.
ADS1282
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full-scale input voltage V
IN
= (AINP – AINN) ±V
REF
/(2 × PGA) V
Absolute input range AINP or AINN AVSS + 0.7 AVDD – 1.25 V
PGA input voltage noise density 5 nV/√Hz
Differential input impedance
(2)
1 GΩ
Common-mode input impedance 100 MΩ
Input bias current 1 nA
Crosstalk f = 31.25Hz –135 dB
MUX on-resistance 30 Ω
PGA OUTPUT (CAPP, CAPN)
Absolute output range AVSS + 0.4 AVDD – 0.4 V
PGA differential output impedance 600 Ω
Output impedance tolerance ±10 %
External bypass capacitance 10 100 nF
High-resolution mode 55 kΩ
Modulator differential input impedance
Low-power mode 110 kΩ
AC PERFORMANCE
High-resolution mode 120 124
Signal-to-noise ratio
(3)
SNR dB
Low-power mode 117 121
High-resolution mode
PGA = 1...16 –122 –114
PGA = 32 –117 –110 dB
PGA = 64 –115
Total harmonic distortion
(4)
THD
Low-power mode
PGA = 1...16 –122 –114
PGA = 32 –113 –108 dB
PGA = 64 –109
Spurious-free dynamic dB
SFDR 123
range
DC PERFORMANCE
Resolution No missing codes 31 Bits
FIR filter mode 250 4000 SPS
Data rate f
DATA
Sinc filter mode 8000 128,000 SPS
Integral nonlinearity (INL)
(5)
Differential input 0.00005 0.0004 % FSR
(6)
Offset error 50 200 mV
Offset error after calibration
(7)
Shorted input 1 mV
Offset drift 0.02 mV/°C
High-resolution mode –1.5 –1.0 –0.5 %
Gain error
(8)
Low-power mode –1 –0.5 0 %
Gain error after calibration
(7)
0.0002 %
(1) f
CLK
= system clock.
(2) Input impedance is improved by disabling input chopping (CHOP bit = 0).
(3) V
IN
= 20mV
DC
/PGA; see Table 1.
(4) V
IN
= 31.25Hz, –0.5dBFS.
(5) Best-fit method.
(6) FSR: Full-scale range = ±V
REF
/(2 × PGA).
(7) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).
(8) The PGA output impedance and the modulator input impedance results in –1% systematic gain error (high-resolution mode) and –0.5%
error (low-power mode).
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): ADS1282
ADS1282
SBAS418G –SEPTEMBER 2007–REVISED MAY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, f
CLK
(1)
= 4.096MHz,
VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, High-Resolution Mode, and f
DATA
=
1000SPS, unless otherwise noted.
ADS1282
PARAMETER CONDITIONS MIN TYP MAX UNIT
DC PERFORMANCE (continued)
PGA = 1 2 ppm/°C
Gain drift
PGA = 16 9 ppm/°C
Gain matching
(9)
0.3 0.8 %
Common-mode rejection f
CM
= 60Hz
(10)
95 110 dB
AVDD, AVSS 80 90
Power-supply rejection f
PS
= 60Hz
(10)
dB
DVDD 90 115
VOLTAGE REFERENCE INPUTS
(AVDD – AVSS)
Reference input voltage (V
REF
= VREFP – VREFN) 0.5 5 V
+ 0.2
Negative reference input VREFN AVSS – 0.1 VREFP – 0.5 V
Positive reference input VREFP VREFN + 0.5 AVDD + 0.1 V
High-resolution mode 85 kΩ
Reference input impedance
Low-power mode 170 kΩ
DIGITAL FILTER RESPONSE
Passband ripple ±0.003 dB
Passband (–0.01dB) 0.375 × f
DATA
Hz
Bandwidth (–3dB) 0.413 × f
DATA
Hz
High-pass filter corner 0.1 10 Hz
Stop band attenuation
(11)
135 dB
Stop band 0.500 × f
DATA
Hz
Minimum phase filter
(12)
5/f
DATA
Group delay s
Linear phase filter 31/f
DATA
Minimum phase filter 62/f
DATA
Settling time (latency) s
Linear phase filter 62/f
DATA
DIGITAL INPUT/OUTPUT
V
IH
0.8 × DVDD DVDD V
V
IL
DGND 0.2 × DVDD V
V
OH
I
OH
= 1mA 0.8 × DVDD V
V
OL
I
OL
= 1mA 0.2 × DVDD V
Input leakage 0 < V
DIGITAL IN
< DVDD ±10 mA
Clock input f
CLK
1 4.096 MHz
Serial clock rate f
SCLK
f
CLK
/2 MHz
(9) Gain match relative to PGA = 1.
(10) f
CM
is the input common-mode frequency. f
PS
is the power-supply frequency.
(11) Input frequencies in the range of Nf
CLK
/512 ± f
DATA
/2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency
ranges intermodulation = 120dB, typ.
(12) At dc; see Figure 49.
4 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1282
SCLK
DIN
DOUT
t
SCLK
t
SPWH
t
SCDL
t
DIST
t
DIHD
t
SPWL
t
SCDL
t
DOHD
t
DOPD
ADS1282
www.ti.com
SBAS418G –SEPTEMBER 2007–REVISED MAY 2010
ELECTRICAL CHARACTERISTICS (continued)
Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, f
CLK
(1)
= 4.096MHz,
VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, High-Resolution Mode, and f
DATA
=
1000SPS, unless otherwise noted.
ADS1282
PARAMETER CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
AVSS –2.6 0 V
AVDD AVSS + 4.75 AVSS + 5.25 V
DVDD 1.65 3.6 V
High-resolution mode 4.5 6.5 |mA|
Low-power mode 3 4.2 |mA|
AVDD, AVSS current
Standby mode 1 15 |mA|
Power-down mode 1 15 |mA|
All modes 0.6 0.8 mA
Modulator mode 0.1 mA
DVDD current
Standby mode 25 50 mA
Power-down mode
(13)
1 15 mA
High-resolution mode 25 35 mW
Low-power mode 17 25 mW
Power dissipation
Standby mode 90 250 mW
Power-down mode 10 125 mW
(13) CLK input stopped.
TIMING DIAGRAM
TIMING REQUIREMENTS
At T
A
= –40°C to +85°C and DVDD = 1.65V to 3.6V, unless otherwise noted.
PARAMETER DESCRIPTION MIN MAX UNITS
t
SCLK
SCLK period 2 16 1/f
CLK
t
SPWH, L
SCLK pulse width, high and low
(1)
0.8 10 1/f
CLK
t
DIST
DIN valid to SCLK rising edge: setup time 50 ns
t
DIHD
Valid DIN to SCLK rising edge: hold time 50 ns
t
DOPD
SCLK falling edge to valid new DOUT: propagation delay
(2)
100 ns
t
DOHD
SCLK falling edge to DOUT invalid: hold time 0 ns
Final SCLK rising edge of command to first SCLK rising edge for register read/write
t
SCDL
24 1/f
CLK
data. (Also between consecutive commands.)
(1) Holding SCLK low for 64 DRDY falling edges resets the serial interface.
(2) Load on DOUT = 20pF || 100kΩ.
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): ADS1282
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