1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS
OTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE INTEGRATED
CIRCUITS THEY SHOULD BE PLACED NEAR.
NOTES, UNLESS OTHERWISE SPECIFIED:
1. RESISTANCE VALUES IN OHMS.
2. CAPACTITANCE VALUES IN MICROFARADS.
3. REFERENCE DESIGNATORS USED:
5. OBSERVE THE FOLLOWING LAYOUT NOTES:
1. TOP - SIGNAL ROUTING
2. GROUND PLANE
3. INNER1 - SIGNAL ROUTING
4. VCC3 PLANE (3.3V BOARD)
5. INNER2 - SIGNAL ROUTING
6. INNER3 - SIGNAL ROUTING
7. VCC PLANE 2
8. INNER4 - SIGNAL ROUTING
9. GROUND PLANE
10. BOTTOM - SIGNAL ROUTING
6. BOARD PROPERTIES
B. 50 +/- 5 OHM MATCHED IMPEDANCE
C. OUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATING
D. INNER LAYERS 1.0 OZ CU
E. FR4 BOARD MATERIAL
F. MINIMUM TRACE WIDTH/SPACING 4 MILS
G. MINIMUM VIA SIZE 10/19 MIL
H. LAYER STACKUP:
A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE
SCHEMATIC INDEX
1 DM642 EVM Notes and Contents
2 User Options/Config
3 DM642 Clocks, Reset, Interrupts, Timers, and IIC
4 DM642 EMIF
5 Emulation Headers
6 DM642 Video Ports
7 DM642 PCI/HPI/EMAC
8 DM642 Power Pins
9 SDRAM
10 Expansion EMIF Buffers
11 Flash and Dual UART
12 RS232 Buffers
13 Video Port Expansion Switches
14 Video Port Daugher Card Connector
15 EMIF Daughter Card Connector
16 OSD FPGA
17 OSD FPGA Power
18 Video Decoder 1
19 Video Decoder 2
20 Video Encoder
21 Ethernet
22 PCI
23 AIC23 Audio Interface
24 Power
25 FPGA Power/Reset Circuitry
REV
ENGR
2
REVISION STATUS OF SHEETS
1
11
SH
DATE
1412 13
DATE
ENGR-MGR
MFG
7
DWN
DATE
8
DATE
10
SH
DATE
CHK
RLSE
APPLICATION
REV
35
NEXT ASSY
DATE
6
DATE
9
QA
USED ON
4
15
DCDAAACBAD
BABAC
R.R.P.
T.W.K.
R.R.P.
R.R.P.
C.M.D.
R.R.P.
R.R.P.
03/30/2003
03/30/2003
16 17 18 19 20
21 22 23 24 25 03/30/2003
03/30/2003
03/30/2003
03/30/2003
03/30/2003
REV
SH
A Initial schematic ready for layout.
DESCRIPTIONREV APPROVEDDATE
01/07/03 RRP
Sheet 2: Changed LENDIAN_MODE signal so R221 is a pull-up and S2 provides
a pull-down.
Sheet 3: Swapped DSP_SCL0 and DSP_SDA0 signals going to U16.
Sheet 7: Added series terminations RN28, R246, R247, & R248.
Sheet 11: Routed DC_A[8:6], UART_CSA#, & UART_CSB# to U15.
Sheet 13: Changed bus routed to U53 to VP0D[9:2] and U52 to VP1D[9:2].
Sheet 15: Added pull-up (R241) to DC_ARDY.
Sheet 17: Pin 177 is Ground not VCC
Sheet 20: Changed U36 & U37 to SN74LVC1G125DCKR.
B 04/01/03 RRP
Sheet 2: Changed EMAC_ENABLE to autodect S2 is now 2 position switch.
Sheet 3: Routed FPGALOCK to pullup R101 to lock FPGA programming
Sheet 7: Implemented EMAC_ENABLE Autodetect on U41-1A, added R249
Sheet 11: Added TCE2# ,TCE3#, SOE3# to U15 Decoder.
Sheet 16: Swapped pins 141 and 149 on FPGA for HDTV speed paths, changed
fpga to -7 part
Sheet 17: Added AND Gate U55 to Lock FPGA programming, changed FPGA to -7
Sheet 20: Swapped Red and Blue on VGA Connector. Removed R102,R129,R183
Sheet 22: Added R250 for HPI option
RRP05/15/03
C
ACAAB
CCDDD
D
Sheet 10: Changed Buffers U2,U3,U4,U5 to non-holder type SN74LVT16245B
Sheet 18: Changed crystal capacitors C168 and C169 from 18pF to 33 pF
Sheet 19: Changed crystal capacitors C288 and C289 from 18pF to 33 pF
Sheet 20: Changed Value on output termination R82,R130,R184 from 75 ohms
to 82 ohms.
08/01/03 RRP
D 08/01/04 RRPSheet 03: Changed Oscillator U26 to 60MHz. For -0003 version of 506840
506842
D
DM642 Evaluation Module
B
125
Monday, September 20, 2004
SPECTRUM DIGITAL INCORPORATED
Title
Size Document Number Rev
Date: Sheet
of
剩余24页未读，继续阅读
评论1