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Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services.
Printed on recycled paper
ii Altera Corporation
Altera Corporation iii
Preliminary
Contents
Chapter Revision Dates ............................................................................ xi
About This Handbook ............................................................................. xiii
Introduction ............................................................................................................................................ xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiv
Section I. Memory
Revision History ....................................................................................................................... Section I–1
Chapter 1. SDRAM Controller with Avalon Interface
Core Overview ....................................................................................................................................... 1–1
Functional Description .......................................................................................................................... 1–1
Avalon Interface ............................................................................................................................... 1–2
Off-Chip SDRAM Interface ............................................................................................................. 1–3
Signal Timing & Electrical Characteristics .............................................................................. 1–3
Synchronization .......................................................................................................................... 1–3
Sharing Pins with Other Avalon Tristate Devices ................................................................. 1–3
Performance Considerations .......................................................................................................... 1–4
Open Row Management ........................................................................................................... 1–4
Sharing Data & Address Pins .................................................................................................... 1–4
Hardware Design & Target FPGA .......................................................................................... 1–5
Device & Tools Support ........................................................................................................................ 1–5
Memory Profile Tab ......................................................................................................................... 1–7
Timing Tab ........................................................................................................................................ 1–8
Hardware Simulation Considerations ................................................................................................ 1–9
SDRAM Controller Simulation Model ..................................................................................... 1–9
SDRAM Memory Model .......................................................................................................... 1–10
Using the Generic Memory Model ......................................................................................... 1–10
Using the SDRAM Manufacturer’s Memory Model ............................................................ 1–10
Software Programming Model .......................................................................................................... 1–13
Chapter 2. Common Flash Interface Controller Core with Avalon Interface
Core Overview ....................................................................................................................................... 2–1
Functional Description .......................................................................................................................... 2–1
Device & Tools Support ........................................................................................................................ 2–2
Instantiating the Core in SOPC Builder ............................................................................................. 2–2
Attributes Tab ................................................................................................................................... 2–2
iv Altera Corporation
Preliminary
Quartus II Handbook, Volume 5
Presets Settings ............................................................................................................................ 2–3
Size Settings ................................................................................................................................. 2–3
Board Info ..................................................................................................................................... 2–3
Timing Tab ........................................................................................................................................ 2–4
Software Programming Model ............................................................................................................ 2–4
HAL System Library Support ......................................................................................................... 2–4
Limitations ................................................................................................................................... 2–4
Software Files .................................................................................................................................... 2–5
Chapter 3. EPCS Device Controller Core with Avalon Interface
Core Overview ....................................................................................................................................... 3–1
Functional Description .......................................................................................................................... 3–2
Avalon Slave Interface & Registers ................................................................................................ 3–3
Device & Tools Support ........................................................................................................................ 3–4
Instantiating the Core in SOPC Builder ............................................................................................. 3–4
Software Programming Model ............................................................................................................ 3–5
HAL System Library Support ......................................................................................................... 3–5
Software Files .................................................................................................................................... 3–5
Chapter 4. DMA Controller with Avalon Interface
Core Overview ....................................................................................................................................... 4–1
Functional Description .......................................................................................................................... 4–1
Setting Up DMA Transactions ....................................................................................................... 4–2
The Master Read & Write Ports ...................................................................................................... 4–3
Address Incrementing ..................................................................................................................... 4–3
Instantiating the Core in SOPC Builder ............................................................................................. 4–4
DMA Parameters (Basic) ................................................................................................................. 4–4
Width of the DMA Length Register ......................................................................................... 4–4
Construct FIFO from Registers vs. Construct FIFO from Memory Blocks ......................... 4–5
Advanced Options ........................................................................................................................... 4–5
Allowed Transactions ................................................................................................................. 4–5
Software Programming Model ............................................................................................................ 4–5
HAL System Library Support ......................................................................................................... 4–5
ioctl() Operations ........................................................................................................................ 4–6
Limitations ................................................................................................................................... 4–7
Software Files .................................................................................................................................... 4–7
Register Map ..................................................................................................................................... 4–7
status Register .............................................................................................................................. 4–8
readaddress Register .................................................................................................................. 4–9
writeaddress Register ................................................................................................................. 4–9
length Register ............................................................................................................................. 4–9
control Register ........................................................................................................................... 4–9
Interrupt Behavior .......................................................................................................................... 4–11
Altera Corporation v
Preliminary
Contents
Section II. Communications
Revision History ..................................................................................................................... Section II–1
Chapter 5. JTAG UART Core with Avalon Interface
Core Overview ....................................................................................................................................... 5–1
Functional Description .......................................................................................................................... 5–1
Avalon Slave Interface & Registers ................................................................................................ 5–2
Read & Write FIFOs ......................................................................................................................... 5–2
JTAG Interface .................................................................................................................................. 5–3
Host-Target Connection .................................................................................................................. 5–3
Device Support & Tools ........................................................................................................................ 5–4
Instantiating the Core in SOPC Builder ............................................................................................. 5–4
Configuration Tab ............................................................................................................................ 5–4
Write FIFO Settings ..................................................................................................................... 5–5
Read FIFO Settings ..................................................................................................................... 5–5
Simulation Settings .......................................................................................................................... 5–6
Simulated Input Character Stream ........................................................................................... 5–6
Prepare Interactive Windows .................................................................................................... 5–6
Hardware Simulation Considerations ................................................................................................ 5–7
Software Programming Model ............................................................................................................ 5–7
HAL System Library Support ......................................................................................................... 5–7
Driver Options: Fast vs. Small Implementations ................................................................... 5–9
ioctl() Operations ...................................................................................................................... 5–10
Software Files .................................................................................................................................. 5–11
Accessing the JTAG UART Core via a Host PC ......................................................................... 5–11
Register Map ................................................................................................................................... 5–11
Data Register .............................................................................................................................. 5–12
Control Register ........................................................................................................................ 5–13
Interrupt Behavior .......................................................................................................................... 5–13
Chapter 6. UART Core with Avalon Interface
Core Overview ....................................................................................................................................... 6–1
Avalon Slave Interface & Registers ................................................................................................ 6–2
RS-232 Interface ................................................................................................................................ 6–3
Transmitter Logic ............................................................................................................................. 6–3
Receiver Logic ................................................................................................................................... 6–4
Baud Rate Generation ...................................................................................................................... 6–4
Device Support & Tools ........................................................................................................................ 6–4
Instantiating the Core in SOPC Builder ............................................................................................. 6–4
Configuration Settings ..................................................................................................................... 6–5
Baud Rate Options ...................................................................................................................... 6–5
Data Bits, Stop Bits, Parity ......................................................................................................... 6–6
Flow Control ................................................................................................................................ 6–6
Streaming Data (DMA) Control ................................................................................................ 6–7
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