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Topmicro Electronics Corp. reserves the right to make changes without further notice to any products herein to improve reliability,
function or design. Topmicro Electronics Corp. does not assume any liability arising out of the application or use of any product or
circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Topmicro Electronics Corp.
products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or othe r a pplications i ntended to sup port or sustain life, or for an y other ap plication in which th e failu re of the Topmicro
Electronics Corp. product could create a si tuation whe re personal i njury or d eath may occu r. Should Bu yer p urchase or use
Topmicro Electronics Corp. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Topmicro
Electronics Corp. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages,
and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Topmicro Electronics Corp. was negligent regarding the
design or manufacture of the part.
User Guide — TH103-G V2.5
Topmicro Electronics Corp.
NON-DISCLOSURE AGREEMENT REQUIRED
1
High Speed 10-bits LVDS Transmitter
TH103-G V2.5
User Guide — TH103-G V2.5
Topmicro Electronics Corp.
NON-DISCLOSURE AGREEMENT REQUIRED 2
Section 1 Introduction
1.1 Overview
The TH103-G LVDS transmitter supports transmission between the host and the flat panel display up to
SXGA+ resolutions. The transmitter converts 32 bits (10-bits/color, 2 dummy bits) of CMOS/TTL data
and 3 control bits into 5 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock
rate of 135MHz, each LVDS differential data pair speed is 945Mbps, providing a total throughput of
4.7Gbps. The transmitter can be configured to input clock rising edge or falling edge strobe through an
external pin.
1.2 Features
The TH103-G includes the following distinctive features:
• Support 8MHz to 135MHz clock rates for NTSC to SXGA+ resolution
• Up to 4.7Gbps bandwidth
• PLL requires no external components
• Cycle-to-cycle jitter rejection
• Programmable data and control strobe select
• Reduced swing LVDS supported
• Power down mode supported
• Compatible with THine THC63LVD103
• Single 3.3V CMOS design
• 64-pin LQFP (Pb Free, compliant to JEDEC/IPC J-STD-006)
User Guide — TH103-G V2.5
Topmicro Electronics Corp.
NON-DISCLOSURE AGREEMENT REQUIRED 3
Section 2 Overview
2.1 Block Diagram
Figure 2-1 Block Diagram of LVDS Transmitter TH103-G
CLKIN
TA0 - TA6
TB0 - TB6
TC0 - TC6
TTL INPUT LATCH
PLL
TD0 - TD6
TE0 - TE6
PWR_UP
DATA SERIALIZER
35
TA+/-
TB+/-
TC+/-
TD+/-
TE+/-
CLK+/-
RS
R_F
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