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Application Report
SCAA062 – March 2003
1
DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CM
Kal Mustafa / Chris Sterzik High Performance Analog
ABSTRACT
This report describes various methods of interfacing different logic levels. The focus is dc-
coupling between the following differential signaling: LVPECL (low-voltage positive-
referenced emitter coupled logic), LVDS (low-voltage differential signals), HSTL (high-
speed transceiver logic), and CML (current-mode logic). The report discusses sixteen
various interface cases between the aforementioned differential signaling levels.
Contents
1 AC-Coupling..................................................................................................................................2
1.1 LVPECL..................................................................................................................................3
1.2 LVDS ....................................................................................................................................7
1.3 CML ..................................................................................................................................11
1.4 HSTL ..................................................................................................................................13
2 References ..................................................................................................................................15
Figures
Figure 1. Input and Output Parameters..........................................................................................2
Figure 2. LVPECL to LVPECL..........................................................................................................3
Figure 3. LVPECL to LVPECL..........................................................................................................4
Figure 4. LVPECL to LVDS..............................................................................................................4
Figure 5. LVPECL to LVDS..............................................................................................................5
Figure 6. LVPECL to CML................................................................................................................5
Figure 7. LVPECL to CML Converter ..............................................................................................6
Figure 8. LVPECL to HSTL ..............................................................................................................6
Figure 9. LVDS to LVPECL..............................................................................................................7
Figure 10. LVDS to LVPECL..............................................................................................................8
Figure 11. LVDS to LVDS Without On-Chip Termination ................................................................8
Figure 12. LVDS to LVDS With On-Chip Termination......................................................................9
Figure 13. LVDS to CML Converter...................................................................................................9
Figure 14. LVDS to HSTL.................................................................................................................10
Figure 15. CML to LVPECL Translator............................................................................................11
Figure 16. CML to LVDS ..................................................................................................................11
Figure 17. CML to CML....................................................................................................................12
Figure 18. CML to HSTL...................................................................................................................13
Figure 19. HSTL to LVPECL Converter...........................................................................................13
Figure 20. HSTL to LVDS.................................................................................................................14
Figure 21. HSTL to CML Translator ................................................................................................14
Figure 22. HSTL to HSTL.................................................................................................................15
Tables
Table 1. Typical LVPECL, LVDS, HSTL, and CML Outputs..........................................................2
Table 2. Typical LVPECL, LVDS, CML, and HSTL Input Levels...................................................2
Table 3. Interface Table..................................................................................................................3
SCAA062
2 DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CM
1 AC-Coupling
DC-coupling is used in a system when there is a need for a wide bandwidth, or when dc-
unbalanced code is used. Both interfaces must have the same ground potential on the same
board or system. DC-coupling directly connects the components together without any coupling
capacitors. Among the advantages of dc-coupling are: simple board design, no dc-wander
issues, and it is useful in all coded-data streams including SONET and NRZ data applications.
One disadvantage of dc-coupling is that it requires careful power supply design. Figure1,
Table 1, and Table 2 provide the I/O levels for these differential signals.
Receiver
V
IH
(MAX)
V
IH
(MIN)
V
IL
(MAX)
V
IL
(MIN)
Driver
V
OH
(MAX)
V
OH
(MIN)
I
OH
(MAX)
V
OL
(MAX)
V
OL
(MIN)
I/O Parameters
VCM
Figure 1. Input and Output Parameters
Table 1. Typical LVPECL, LVDS, HSTL, and CML Outputs
Output LVPECL LVDS HSTL CML
V
OH
(Min)
2.275 V 1.249 VDDQ
1
-0.4 V
CC
2
V
OL
(Max)
1.68 V 1.252 0.4 V
CC
-0.4V
Table 2. Typical LVPECL, LVDS, CML, and HSTL Input Levels
Input LVPECL LVDS HSTL CML
V
IH
(Min) 2.135 V 1.249 VRef + 0.2 V
CC
VRef or VCM 2 1.2 0.75 V
CC
-0.2V
V
IL
(Max) 1.825 V 1.252 VRef -0.2 V
CC
-0.4V
V
ID
(Min) 310 mV 200 mV 400 mV 400 mV
1
VDDQ = 1.5 V ±10%
2
V
CC
= 3.3 V ±10%
SCAA062
DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CM 3
Table 3. Interface Table
TO
LVPECL LVDS CML HSTL
LVPECL
See Figure 3
See Figure 4 or Figure 5 See Figure 6 or Figure 7 See Figure 8
LVDS
See Figure 9
or Figure 10 See Figure 11 or Figure 12 See Figure 13 See Figure 14
CML
See Figure 15
See Figure 16 or See Figure 17 See Figure 18
FROM
HSTL
See Figure 19
See Figure 20 See Figure 21 See Figure 22
1.1 LVPECL
e.g.,
CDC111
CDCVF111
CDCLVP110
Z
O
=50Ω
ΩΩ
Ω
Z
O
=50Ω
ΩΩ
Ω
V
C
C
V
C
C
130
Ω
Ω
Ω
Ω
130
Ω
Ω
Ω
Ω
83
Ω
Ω
Ω
Ω
83
Ω
Ω
Ω
Ω
LVPECL
Driver
LVPECL
Receiver
Figure 2. LVPECL to LVPECL
PECL and LVPECL are normally terminated though 50 Ω to (V
CC
- 2 V). Most systems normally
do not have dual power supplies of both 3.3 V and 1.3 V; therefore Figures 2 and Figure 3 show
alternative methods to terminate LVPECL output signals. The pullup and pulldown combination
terminates the 50-Ω transmission line and establish the LVPECL common-mode voltage of 2 V
at the receiver.
SCAA062
4 DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CM
e.g.,
CDC111
CDCVF111
CDCLVP110
Z
O
=50Ω
ΩΩ
Ω
Z
O
=50Ω
ΩΩ
Ω
R2
R1
R3
LVPECL
Driver
LVPECL
Receiver
(V
CC
-2V)
Note:
For V
CC
=3.3V,useR1=R2=R3=50Ω
ΩΩ
Ω
For V
CC
=2.5V,useR1=R2=50 Ω,
50 Ω, 50 Ω,
50 Ω, R3 = 22 Ω
= 22 Ω= 22 Ω
= 22 Ω
Figure 3. LVPECL to LVPECL
The Y-termination in Figure 3 is another alternative to LVPECL termination where a VTT supply
is not readily available. This scheme saves one resistor over the scheme in Figure 2.
e.g.,
CDC111
CDCVF111
SN65LVDS101
CDCLVP110
e.g.,
SN65LVDS104
SN65LVDS108
SN65LVDS116
Z
O
=50Ω
ΩΩ
Ω
Z
O
=50Ω
ΩΩ
Ω
130
Ω
Ω
Ω
Ω
33 Ω
ΩΩ
Ω
3
.
3
V
LVDS
Receiver
3
.
3
V
130
Ω
Ω
Ω
Ω
50
Ω
Ω
Ω
Ω
33 Ω
ΩΩ
Ω
50
Ω
Ω
Ω
Ω
LVPECL
Driver
Figure 4. LVPECL to LVDS
The 33-Ω resistor is usually required when the LVPECL output is too high for the LVDS receiver
input stage. For the LVDS receivers listed above, it is not required and Figure 5 is
recommended.
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