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Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services.
ii Altera Corporation
Preliminary
Altera Corporation iii
Preliminary
Contents
Chapter Revision Dates ........................................................................... xi
About this Handbook ............................................................................. xiii
How to Find Information ..................................................................................................................... xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiv
Section I. Cyclone FPGA Family Data Sheet
Revision History ....................................................................................................................... Section I–1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–2
Chapter 2. Cyclone Architecture
Functional Description .......................................................................................................................... 2–1
Logic Array Blocks ................................................................................................................................ 2–3
LAB Interconnects ............................................................................................................................ 2–3
LAB Control Signals ......................................................................................................................... 2–4
Logic Elements ....................................................................................................................................... 2–5
LUT Chain & Register Chain .......................................................................................................... 2–7
addnsub Signal ................................................................................................................................. 2–7
LE Operating Modes ........................................................................................................................ 2–7
MultiTrack Interconnect ..................................................................................................................... 2–12
Embedded Memory ............................................................................................................................. 2–18
Memory Modes ............................................................................................................................... 2–18
Parity Bit Support ........................................................................................................................... 2–20
Shift Register Support .................................................................................................................... 2–20
Memory Configuration Sizes ........................................................................................................ 2–21
Byte Enables .................................................................................................................................... 2–23
Control Signals & M4K Interface .................................................................................................2–23
Independent Clock Mode .............................................................................................................. 2–25
Input/Output Clock Mode ........................................................................................................... 2–25
Read/Write Clock Mode ............................................................................................................... 2–28
Single-Port Mode ............................................................................................................................ 2–29
Global Clock Network & Phase-Locked Loops ............................................................................... 2–29
Global Clock Network ................................................................................................................... 2–29
Dual-Purpose Clock Pins .............................................................................................................. 2–31
iv Altera Corporation
Preliminary
Cyclone Device Handbook, Volume 1
Combined Resources ..................................................................................................................... 2–31
PLLs .................................................................................................................................................. 2–32
Clock Multiplication & Division .................................................................................................. 2–35
External Clock Inputs .................................................................................................................... 2–36
External Clock Outputs ................................................................................................................. 2–36
Clock Feedback ............................................................................................................................... 2–37
Phase Shifting ................................................................................................................................. 2–37
Lock Detect Signal .......................................................................................................................... 2–37
Programmable Duty Cycle ........................................................................................................... 2–38
Control Signals ................................................................................................................................ 2–38
I/O Structure ........................................................................................................................................ 2–39
External RAM Interfacing ............................................................................................................. 2–46
DDR SDRAM & FCRAM .............................................................................................................. 2–46
Programmable Drive Strength .....................................................................................................2–49
Open-Drain Output ........................................................................................................................ 2–50
Slew-Rate Control .......................................................................................................................... 2–51
Bus Hold .......................................................................................................................................... 2–51
Programmable Pull-Up Resistor .................................................................................................. 2–51
Advanced I/O Standard Support ................................................................................................ 2–52
LVDS I/O Pins ................................................................................................................................ 2–54
MultiVolt I/O Interface ................................................................................................................. 2–54
Power Sequencing & Hot Socketing ................................................................................................. 2–55
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5
Configuration ......................................................................................................................................... 3–5
Operating Modes .............................................................................................................................. 3–6
Configuration Schemes ................................................................................................................... 3–6
Chapter 4. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 4–1
Power Consumption ............................................................................................................................. 4–7
Timing Model ......................................................................................................................................... 4–8
Preliminary & Final Timing ............................................................................................................ 4–9
Performance ...................................................................................................................................... 4–9
Internal Timing Parameters .......................................................................................................... 4–10
External Timing Parameters ......................................................................................................... 4–15
External I/O Delay Parameters .................................................................................................... 4–21
Maximum Input & Output Clock Rates ...................................................................................... 4–27
PLL Timing ...................................................................................................................................... 4–29
Chapter 5. Reference & Ordering Information
Software .................................................................................................................................................. 5–1
Device Pin-Outs ..................................................................................................................................... 5–1
Ordering Information ........................................................................................................................... 5–1
Altera Corporation v
Preliminary
Contents
Section II. Clock Management
Revision History ..................................................................................................................... Section II–1
Chapter 6. Using PLLs in Cyclone Devices
Introduction ............................................................................................................................................ 6–1
Hardware Overview ........................................................................................................................ 6–1
Software Overview .......................................................................................................................... 6–4
Pins & Clock Network Connections .............................................................................................. 6–6
Hardware Features ................................................................................................................................ 6–8
Clock Multiplication & Division .................................................................................................... 6–8
Phase Shifting ................................................................................................................................... 6–9
Programmable Duty Cycle ........................................................................................................... 6–10
External Clock Output ................................................................................................................... 6–11
Control Signals ................................................................................................................................ 6–12
Clock Feedback Modes ....................................................................................................................... 6–13
Normal Mode .................................................................................................................................. 6–14
Zero Delay Buffer Mode ................................................................................................................ 6–14
No Compensation .......................................................................................................................... 6–15
Pins ......................................................................................................................................................... 6–16
Board Layout ........................................................................................................................................ 6–17
VCCA & GNDA ............................................................................................................................. 6–17
Jitter Considerations ...................................................................................................................... 6–19
Specifications ........................................................................................................................................ 6–20
Software Support ................................................................................................................................. 6–20
Quartus II altpll Megafunction ..................................................................................................... 6–20
altpll Input Ports ............................................................................................................................. 6–22
altpll Output Ports ......................................................................................................................... 6–23
MegaWizard Customization ......................................................................................................... 6–23
MegaWizard Page Description .....................................................................................................6–25
Compilation Report ....................................................................................................................... 6–31
Timing Analysis .............................................................................................................................. 6–33
Simulation ....................................................................................................................................... 6–37
Global Clock Network ........................................................................................................................ 6–38
Dedicated Clock Input Pins .......................................................................................................... 6–40
Dual-Purpose Clock I/O Pins ...................................................................................................... 6–40
Combined Sources .......................................................................................................................... 6–41
Conclusion ............................................................................................................................................ 6–43
Section III. Memory
Revision History .................................................................................................................... Section III–1
Chapter 7. On-Chip Memory Implementations Using Cyclone Memory Blocks
Introduction ............................................................................................................................................ 7–1
M4K Memory Features ......................................................................................................................... 7–1
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