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s3c2450 datasheet
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s3c2450 datasheet Around 400MHz @ 1.2V, 533MHz @ TBDV Core, 1.8V/2.5V/3.0V/3.3V ROM/SRAM, 1.8V/2.5V/3.3V mSDR/mDDR/DDR2 SDRAM, 1.8V/2.5V/3.3V external I/O microprocessor with 16KB I/D-Cache/MMU
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S3C2450X
USER’S MANUAL
Preliminary Revision 0.0
REVISION HISTORY
Revision Date Description
0.0 February 18, 2008 Preliminary release
S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW
1-1
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Spec
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1 PRODUCT OVERVIEW
INTRODUCTION
This user’s manual describes SAMSUNG's S3C2450X 16/32-bit RISC microprocessor. SAMSUNG’s S3C2450X
is designed to provide hand-held devices and general applications with low-power, and high-performance micro-
controller solution in small die size. To reduce total system cost, the S3C2450X includes the following
components.
The S3C2450X is developed with ARM926EJ core, 65nm CMOS standard cells and a memory complier. Its low-
power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It
adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).
The S3C2450X offers outstanding features with its CPU core, a 16/32-bit ARM926EJ RISC processor designed
by Advanced RISC Machines, Ltd. The ARM926EJ implements MMU, AMBA BUS, and Harvard cache
architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
By providing a complete set of common system peripherals, the S3C2450X minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-chip functions that are described in
this document include:
• Around 400MHz @ 1.2V, 533MHz @ TBDV Core, 1.8V/2.5V/3.0V/3.3V ROM/SRAM, 1.8V/2.5V/3.3V
mSDR/mDDR/DDR2 SDRAM, 1.8V/2.5V/3.3V external I/O microprocessor with 16KB I/D-Cache/MMU
• External memory controller (mSDR/mDDR/DDR2 SDRAM Control and Chip Select logic) and CF/ATA I/F
controller
• LCD controller (up to 256K color TFT) with LCD-dedicated DMA
• 8-ch DMA controllers with external request pins
• 4-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)
• 2-ch High Speed SPls
• 2 IIC bus interfaces (multi-master support)
• 2 IIS Audio CODEC interfaces (24-bit, port 0 supports 5.1ch, port 1 supports 2ch)
• AC97 CODEC Interface
• 2 High-Speed MMC and SDMMC combo (SD Host 2.0 and MMC protocol 4.2 compatible)
• 2-ch USB Host controller (ver 1.1 Complaint)/1-ch USB Device controller (ver 2.0 Complaint)
• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer
• 10-ch 12-bit ADC and Touch screen interface
• RTC with calendar function
• Camera interface (Max. 8M pixels input support. 2M pixel input support for scaling)
• 174 General Purpose I/O ports / 24-ch external interrupt source
• Power control: Normal, Idle, Stop, Deep Stop and Sleep mode
• On-chip clock generator with PLL
PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR
1-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Spec
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FEATURES
Architecture
• Integrated system for hand-held devices and
general embedded applications.
• 16/32-Bit RISC architecture and powerful
instruction set with ARM926EJ CPU core.
• Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux.
• Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect
of main memory bandwidth and latency on
performance.
• ARM926EJ CPU core supports the ARM debug
architecture.
• Internal Advanced Microcontroller Bus
Architecture (AMBA) (AMBA2.0, AHB/APB).
System Manager
• Little/Big Endian support.
• Two independent memory bus - one for the
ROM/SRAM bus (ROM Bank0~Bank5) and one
for the DRAM bus (mSDR/mDDR/DDR2
SDRAM Bank0~Bank1)
• Address space: 64M bytes for Rom bank0 ~
bank5, 128M bytes for SDRAM bank0 ~ bank1.
• Supports programmable 8/16-bit data bus width
for ROM/SRAM bank and programmable 16/32-
bit data bus width for SDRAM bank
• Fixed bank start address from Rom bank 0 to
bank 5 and SDRAM bank 0 to bank1.
• Eight memory banks:
– Six memory banks for ROM, SRAM, and
others (NAND/CF etc.).
– Two memory banks for Synchronous DRAM.
• Complete Programmable access cycles for all
memory banks.
• Supports external wait signals to expand the bus
cycle.
• Supports self-refresh mode in SDRAM for
power-down.
• Supports various types of ROM for booting
(NOR/NAND Flash, EEPROM, OneNAND and
others).
NAND Flash Boot Loader
• Supports booting from NAND flash memory.
(Only 8bit boot support)
• 64KB for internal SRAM Buffer(8KB internal
buffer for booting)
• Supports storage memory for NAND flash
memory after booting.
• Supports Advanced NAND flash
Cache Memory
• 64-way set-associative cache with I-Cache
(16KB) and D-Cache (16KB).
• 8words length per line with one valid bit and two
dirty bits per line.
• Pseudo random or round robin replacement
algorithm.
• Write-through or write-back cache operation to
update the main memory.
• The write buffer can hold 16 words of data and
four addresses.
Clock & Power Manager
• On-chip MPLL and EPLL:
EPLL generates the clock to operate USB Host,
IIS, UART, etc.
MPLL generates the clock to operate MCU at
maximum 533MHz @ TBD V.
• Clock can be fed selectively to each function
block by software.
• Power mode: Normal, Idle, Stop, Deep Stop and
Sleep mode
Normal mode: Normal operating mode
Idle mode: The clock for only CPU is stopped.
Stop mode: All clocks are stopped.
Deep Stop mode: CPU power is gated and all
clocks are stopped.
Sleep mode: The Core power including all
peripherals is shut down.
• Woken up by EINT[15:0] or RTC alarm & tick
interrupt from (Deep)Sleep mode and STOP
mode.
S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW
1-3
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Spec
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FEATURES (Continued)
Interrupt Controller
• 77 Interrupt sources
(One Watch dog timer, 5 timers, 12 UARTs, 24
external interrupts, 8 DMA, 2 RTC, 2 ADC, 1 IIC,
2 SPI, 2 SDI, 2 USB, 4 LCD, 1 Battery Fault, 1
NAND, 1 CF, 1 AC97 and 2 CAM I/F, 2 I2S, 2
PCM, 1 2D)
• Level/Edge mode on external interrupt source
• Programmable polarity of edge and level
• Supports Fast Interrupt request (FIQ) for very
urgent interrupt request
Timer with Pulse Width Modulation (PWM)
• 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal
timer with DMA-based or interrupt-based
operation
• Programmable duty cycle, frequency, and
polarity
• Dead-zone generation
• Supports external clock sources
RTC (Real Time Clock)
• Full clock feature: msec, second, minute, hour,
date, day, month, and year
• 32.768 KHz operation
• Alarm interrupt
• Time tick interrupt
General Purpose Input/Output Ports
• 24 external interrupt ports
• 174 Multiplexed input/output ports
DMA Controller
• 8-ch DMA controller
• Supports memory to memory, IO to memory,
memory to IO, and IO to IO transfers
• Burst transfer mode to enhance the transfer rate
TFT(Thin Film Transistor) Color Displays Feature
• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette
color displays for color TFT
• Supports 16, 24 bpp non-palette true-color
displays for color TFT
• Supports maximum 16M color TFT at 24 bpp
mode
• Supports multiple screen size
– Typical actual screen size: 640x480, 320x240,
160x160, and others.
– Maximum frame buffer size is 4Mbytes.
– Maximum virtual screen size in 64K color
mode: 2048x2048, and others
• Support 2 overlay windows for TFT
Camera Interface
• ITU-R BT 601/656 8-bit mode support
• DZI (Digital Zoom In) capability
• Programmable polarity of video sync signals
• Max. 4096x4096 pixels input support
(2048x2048 pixel input support for scaling)
• Image mirror and rotation (X-axis mirror, Y-axis
mirror, and 180° rotation)
• Camera output format (RGB 16/24-bit and
YCbCr 4:2:0/4:2:2 format)
UART
• 4-channel UART with DMA-based or interrupt-
based operation
• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit/receive (Tx/Rx)
• Supports external clocks for the UART operation
(UEXTCLK)
• Programmable baud rate
• Supports IrDA 1.0
• Loopback mode for testing
• Each channel has internal 64-byte Tx FIFO and
64-byte Rx FIFO.
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