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Verilog Coding Style for Efficient Digital Design
Kapil Batra Mohammad Suhaib Husain
STMicroelectronics Ltd., India msuhaib@hotmail.com
Kapil.batra@st.com
Abstract: In this paper, we discuss efficient coding and design styles using verilog. This can be
immensely helpful for any digital designer initiating designs. Here, we address different problems ranging
from RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All these
problems are accompanied by an example to have a better idea, and these can be taken care off if these
coding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,
here we try to cover a few of them.
1. Reading a variable before assigning - Simulation and Synthesis mismatch
Non-Blocking statements within the always block are executed sequentially. This becomes an issue when
variables are used in the always block. Variables may be used in some conditional expression or on the
right hand side of an assignment statement besides being assigned some value. Now if they are used prior
to being assigned, a mismatch may occur in simulation and synthesis. For pre-synthesis simulation, that
variable will contain the value assigned to it in the previous pass but it may not happen in gate level
simulation.
This can be illustrated by means of a very simple example. In module example1, “Z” is declared as a
register. It is being used in the right hand side of an assignment statement before being assigned a value in
the next statement. Register “Z” will hold the value of the previous pass until the assignment statement for
“Z” is executed, thus, output “Q” will be assigned a stale value in the current pass. The module example1
was simulated using VCS and the results are as shown in Fig.1a. It is clearly understood by seeing the
waveform that by change in any input, output “Q” gets the stale value assigned to register “Z” in the
previous pass.
module example1 (A, B, Q);
input A, B;
output Q;
reg Z;
always @(A, B, Z)
begin
Q = Z;
Z = A | B;
end
endmodule
Fig. 1a
Now when this module example1 is synthesized, a simple OR gate is generated. And when we apply the
same stimulus to the inputs “A” and “B”, we get the waveform as shown in Fig. 1b, which is nothing but a
simple OR gate.
Q
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