AT89S51芯片手册.pdf_at89s51手册

芯片手册

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Features

• Compatible with MCS

-51

Products

• 4K Bytes of In-System Programmable (ISP) Flash Memory

– Endurance: 10,000 Write/Erase Cycles

• 4.0V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 128 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-bit Timer/Counters

• Six Interrupt Sources

• Full Duplex UART Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Watchdog Timer

• Dual Data Pointer

• Power-off Flag

• Fast Programming Time

• Flexible ISP Programming (Byte and Page Mode)

• Green (Pb/Halide-free) Packaging Option

1. Description

The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K

bytes of In-System Programmable Flash memory. The device is manufactured using

Atmel’s high-density nonvolatile memory technology and is compatible with the indus-

try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program

memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-

grammer. By combining a versatile 8-bit CPU with In-System Programmable Flash on

a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a

highly-flexible and cost-effective solution to many embedded control applications.

The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes

of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a

five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,

and clock circuitry. In addition, the AT89S51 is designed with static logic for operation

down to zero frequency and supports two software selectable power saving modes.

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and

interrupt system to continue functioning. The Power-down mode saves the RAM con-

tents but freezes the oscillator, disabling all other chip functions until the next external

interrupt or hardware reset.

8-bit

Microcontroller

with 4K Bytes

In-System

Programmable

Flash

AT89S51

2487D–MICRO–6/08

AT89S51

4. Pin Description

4.1 VCC

Supply voltage.

4.2 GND

Ground.

4.3 Port 0

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL

inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses

to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-

ing program verification. External pull-ups are required during program verification.

4.4 Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-

nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low

will source current (I

) because of the internal pull-ups.

Port 1 also receives the low-order address bytes during Flash programming and verification.

4.5 Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-

nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low

will source current (I

) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and dur-

ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this

application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external

data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special

Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash program-

ming and verification.

4.6 Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-

Port Pin Alternate Functions

P1.5 MOSI (used for In-System Programming)

P1.6 MISO (used for In-System Programming)

P1.7 SCK (used for In-System Programming)

2487D–MICRO–6/08

AT89S51

nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low

will source current (I

) because of the pull-ups.

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89S51, as shown in the fol-

lowing table.

4.7 RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets

the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DIS-

RTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of

bit DISRTO, the RESET HIGH out feature is enabled.

4.8 ALE/PROG

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during

accesses to external memory. This pin is also the program pulse input (PROG

) during Flash

programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be

used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-

ing each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,

ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.

Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

4.9 PSEN

Program Store Enable (PSEN) is the read strobe to external program memory.

When the AT89S51 is executing code from external program memory, PSEN

is activated twice

each machine cycle, except that two PSEN

activations are skipped during each access to exter-

nal data memory.

4.10 EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch

code from external program memory locations starting at 0000H up to FFFFH. Note, however,

that if lock bit 1 is programmed, EA

will be internally latched on reset.

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0

(external interrupt 0)

P3.3 INT1

(external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR

(external data memory write strobe)

P3.7 RD

(external data memory read strobe)

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