4.3.1 Power-up/Wake-up in Buck Configuration........................................................... 56
4.3.2 Power-up/Wake-up in Boost Configuration ......................................................... 58
4.3.3 Go-to-Sleep and Refresh Bandgap ..................................................................... 59
4.4 OTP Memory Layout ........................................................................................................... 60
4.4.1 OTP Header ......................................................................................................... 60
4.4.2 Configuration Script ............................................................................................. 62
4.5 BootROM Sequence ........................................................................................................... 63
5 Reset ............................................................................................................................................. 67
5.1 Introduction ......................................................................................................................... 67
5.2 Architecture ......................................................................................................................... 67
5.2.1 POR, HW, and SW Reset .................................................................................... 67
5.2.2 POR Functionality ................................................................................................ 69
5.2.2.1 POR Timer Clock ............................................................................. 69
5.2.2.2 RST Pad .......................................................................................... 69
5.2.2.3 POR from GPIO ............................................................................... 69
5.2.3 POR Timing Diagram ........................................................................................... 69
5.2.4 POR Considerations ............................................................................................ 70
5.3 Programming ....................................................................................................................... 70
6 Arm Cortex-M0+ ........................................................................................................................... 71
6.1 Introduction ......................................................................................................................... 71
6.2 Architecture ......................................................................................................................... 72
6.2.1 Interrupts .............................................................................................................. 72
6.2.2 System Timer (systick) ........................................................................................ 74
6.2.3 Wake-Up Interrupt Controller ............................................................................... 74
6.3 Programming ....................................................................................................................... 74
7 AMBA Bus .................................................................................................................................... 75
7.1 Introduction ......................................................................................................................... 75
7.2 Architecture ......................................................................................................................... 75
7.3 Programming ....................................................................................................................... 76
8 Memory Map................................................................................................................................. 77
9 Memory Controller ...................................................................................................................... 79
9.1 Introduction ......................................................................................................................... 79
9.2 Architecture ......................................................................................................................... 79
9.2.1 Arbitration ............................................................................................................ 80
10 Clock Generation ......................................................................................................................... 81
10.1 Clock Tree ........................................................................................................................... 81
10.1.1 General Clock Constraints ................................................................................... 83
10.2 Crystal Oscillators ............................................................................................................... 83
10.2.1 Frequency Control (32 MHz Crystal) ................................................................... 83
10.2.2 Automated Trimming and Settling Notification .................................................... 84
10.3 RC Oscillators ..................................................................................................................... 85
10.3.1 Frequency Calibration .......................................................................................... 86
11 OTP Controller ............................................................................................................................. 87
11.1 Introduction ......................................................................................................................... 87
11.2 Architecture ......................................................................................................................... 87
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