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usb2.0 IP CORE
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更新于2023-03-03
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USB 2.0 开发的参考资料 内涵usb的开发内核 易于理解Usb的协议
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Features
• USB Specification Rev. 2.0 com-
pliant
• Supports up to 127 devices and 8
downstream ports
• Compliant with EHCI Rev. 1.0
specification
• OHCI companion processor for
UBS 1.1 transfers
• Supports 16-bit UTMI and 8-bit
ULPI interfaces
• Direct addressing of all IP Core
registers from PCI, Custom, or
AHB bus
• DMA controller supports high-
speed data transfers between
USB Host and PCI/Custom/AHB
host
• Supports 8, 16, 32-bit PCI/Cus-
tom/AHB bus
• Optional 33 MHz PCI Rev. 2.2
master/target interface
• Optional 133 MHz AHB Rev. 2.0
master/slave interface
• Optional Custom bus interface
USB 2.0 Host IP Core
Overview
The Arasan USB 2.0 Host IP Core is an USB 2.0 specification compliant
host core with optional PCI, Custom, or AHB master/slave interfaces.
The USB 2.0 host core supports 480 Mbit/s in High Speed (HS) mode.
12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS)
mode.
The Arasan USB 2.0 Host IP Core consists of an Enhanced Host Control-
ler Interface (EHCI) and a companion Open Host Controller Interface
(OHCI). The EHCI processor handles HS transactions and is the default
owner of the Root Hub that connects to downstream ports. In a
downstream data transfer, the EHCI sends data to the Host Parallel
Interface Engine (HPIE) for encoding and CRC appending. Data
received by the USB 2.0 Root Hub is forwarded to downstream ports
through the Root Hub. Similarly, FS and LS transactions are handled by
the OHCI, Host Serial Interface Engine (HSIE), and USB 1.1 Root Hub.
The Root Hub performs multiplexing and forwarding of packets
between the downstream ports and USB 2.0/1.1 Root Hubs. Up to 8
downstream ports can be connected to the USB 2.0 Host IP Core.
With the addition of optional ULPI Wrappers, the Arasan USB 2.0 Host
IP Core can be connected directly to standard UTMI or 8-bit ULPI trans-
ceivers.
The Arasan USB 2.0 Host IP Core is an RTL design in Verilog and VHDL
that implements an USB host controller on an ASIC or FPGA. The core
includes RTL code, test scripts and a test environment for full simula-
tion verifications. Licensees include Los Alamos National Labs, Stac-
cato Communications, Focus Semiconductors, etc.
Copyright 2006 Arasan Chip Systems Inc.
Version 1.0
USB 2.0 Certified
USB 2.0 Host IP Core Functional Block Diagram
AMBA
Master/Slave
AHB Bus
PCI Bus
PCI
Master/Target
Custom
Master/Target
Custom Bus
EHCI List Processor OHCI List Processor
Host Serial
Interface Engine
Host Parallel
Interface Engine
USB 2.0 Root Hub USB 1.1 Root Hub
Root Hub
XCVR1, XCVR2, … XCVRN
Prot 1 Prot 2 Prot N Prot 1 Prot 2 Prot N
……
The Arasan USB 2.0 Host IP Core is an
RTL design in Verilog and VHDL that
implements an USB host controller on
an ASIC or FPGA. The core includes RTL
code, test scripts and a test environ-
ment for full simulation verifications.
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