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PCI Express Specification 1.0
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PCIE spec. 1.0 from PCI SIG, it is useful for current status of design, since most of design is PCIE 1.0 or PCIE1.1
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PCI Express
Base Specification
Revision 1.0
April 29, 2002
REVISION REVISION HISTORY DATE
1.0 Initial release. 4/29/02
PCI-SIG disclaims all warranties and liability for the use of this document and the
information contained herein and assumes no responsibility for any errors that may appear
in this document, nor does PCI-SIG make a commitment to update the information
contained herein.
Contact the PCI-SIG office to obtain the latest revision of the specification.
Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be
forwarded to:
Membership Services
www.pcisig.com
E-mail: administration@pcisig.com
Phone: 1-800-433-5177 (Domestic Only)
503-291-2569
Fax: 503-297-1090
Technical Support
techsupp@pcisig.com
DISCLAIMER
This draft Specification is being provided to you for review purposes pursuant to
Article 15.2 of the Bylaws of PCI-SIG. This draft Specification is subject to
amendment until it is officially adopted by the Board of Directors of PCI-SIG. The
Board of Directors may, at its discretion, initiate additional review periods, in which
case you will be notified of the same. Pursuant to Article 14 of the Bylaws, this draft
Specification is to be considered PCI-SIG Confidential until adopted by the Board of
Directors.
All product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
Copyright © 2002 PCI-SIG
PCI EXPRESS BASE SPECIFICATION, REV 1.0
3
Contents
PREFACE........................................................................................................................17
O
BJECTIVE OF THE SPECIFICATION.................................................................................18
D
OCUMENT ORGANIZATION...........................................................................................18
D
OCUMENTATION CONVENTIONS...................................................................................19
T
ERMS AND ABBREVIATIONS .........................................................................................20
R
EFERENCE DOCUMENTS ...............................................................................................25
1. INTRODUCTION...................................................................................................27
1.1. A T
HIRD GENERATION I/O INTERCONNECT .......................................................27
1.2. PCI E
XPRESS LINK.............................................................................................29
1.3. PCI E
XPRESS FABRIC TOPOLOGY ......................................................................30
1.3.1. Root Complex............................................................................................31
1.3.2. Endpoints...................................................................................................32
1.3.3. Switch........................................................................................................33
1.3.4. PCI Express-PCI Bridge...........................................................................34
1.4. PCI E
XPRESS FABRIC TOPOLOGY CONFIGURATION ...........................................34
1.5. PCI E
XPRESS LAYERING OVERVIEW..................................................................35
1.5.1. Transaction Layer .....................................................................................36
1.5.2. Data Link Layer ........................................................................................36
1.5.3. Physical Layer...........................................................................................37
1.5.4. Layer Functions and Services ...................................................................37
1.6. A
DVANCED PEER-TO-PEER COMMUNICATION OVERVIEW.................................41
2. TRANSACTION LAYER SPECIFICATION .....................................................43
2.1. TRANSACTION LAYER OVERVIEW......................................................................43
2.2. A
DDRESS SPACES,TRANSACTION TYPES, AND USAGE ......................................44
2.2.1. Memory Transactions................................................................................44
2.2.2. I/O Transactions........................................................................................45
2.2.3. Configuration Transactions ......................................................................45
2.2.4. Message Transactions...............................................................................45
2.3. P
ACKET FORMAT OVERVIEW .............................................................................47
2.4. T
RANSACTION DESCRIPTOR ...............................................................................48
2.4.1. Overview....................................................................................................48
2.4.2. Transaction Descriptor –Transaction ID Field........................................48
2.4.3. Transaction Descriptor – Attributes Field................................................50
2.4.4. Transaction Descriptor – Traffic Class Field...........................................51
2.5. T
RANSACTION ORDERING ..................................................................................52
2.6. V
IRTUAL CHANNEL (VC) MECHANISM..............................................................56
2.6.1. Virtual Channel Identification (VC ID) ....................................................58
2.6.2. VC Support Options ..................................................................................58
2.6.3. TC to VC Mapping ....................................................................................59
PCI EXPRESS BASE SPECIFICATION, REV 1.0
4
2.6.4. VC and TC Rules.......................................................................................60
2.7. T
RANSACTION LAYER PROTOCOL -PACKET DEFINITION AND HANDLING .........61
2.7.1. Transaction Layer Packet Definition Rules ..............................................61
2.7.2. TLP Digest Rules.......................................................................................65
2.7.3. TLPs with Data Payloads - Rules .............................................................66
2.7.4. Requests.....................................................................................................67
2.7.5. Completions...............................................................................................76
2.7.6. Handling of Received TLPs.......................................................................78
2.8. M
ESSAGES..........................................................................................................88
2.8.1. Baseline Messages.....................................................................................88
2.8.2. Advanced Switching Support Message Group ..........................................98
2.9. O
RDERING AND RECEIVE BUFFER FLOW CONTROL............................................99
2.9.1. Overview and Definitions..........................................................................99
2.9.2. Flow Control Rules .................................................................................100
2.10. D
ATA INTEGRITY .........................................................................................109
2.10.1. Introduction.............................................................................................109
2.10.2. ECRC Rules.............................................................................................109
2.11. E
RROR FORWARDING ...................................................................................113
2.11.1. Error Forwarding Usage Model.............................................................113
2.11.2. Rules For Use of Data Poisoning ...........................................................114
2.12. C
OMPLETION TIMEOUT MECHANISM ...........................................................114
2.13. T
RANSACTION LAYER BEHAVIOR IN DL_DOWN STATUS ............................115
2.14. T
RANSACTION LAYER BEHAVIOR IN DL_UP STATUS ..................................116
3. DATA LINK LAYER SPECIFICATION ..........................................................117
3.1. D
ATA LINK LAYER OVERVIEW ........................................................................117
3.2. D
ATA LINK CONTROL AND MANAGEMENT STATE MACHINE...........................119
3.2.1. Data Link Control and Management State Machine Rules.....................120
3.3. FLOW CONTROL INITIALIZATION PROTOCOL....................................................121
3.3.1. Flow Control Initialization State Machine Rules....................................123
3.4. DATA LINK LAYER PACKETS (DLLPS) ............................................................125
3.4.1. Data Link Layer Packet Rules.................................................................125
3.5. DATA INTEGRITY .............................................................................................130
3.5.1. Introduction.............................................................................................130
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter)..130
3.5.3. LCRC and Sequence Number (TLP Receiver) ........................................142
4. PHYSICAL LAYER SPECIFICATION ............................................................149
4.1. I
NTRODUCTION.................................................................................................149
4.2. LOGICAL SUB-BLOCK................................................................................149
4.2.1. Symbol Encoding.....................................................................................150
4.2.2. Framing and Application of Symbols to Lanes.......................................153
4.2.3. Data Scrambling .....................................................................................156
4.2.4. Link Initialization and Training..............................................................157
4.2.5. Link Training and Status State Machine (LTSSM)........................................180
4.2.6. Link Training and Status State Descriptions...........................................183
4.2.7. Clock Tolerance Compensation ..............................................................195
PCI EXPRESS BASE SPECIFICATION, REV 1.0
5
4.2.8. Compliance Pattern.................................................................................197
4.3. E
LECTRICAL SUB-BLOCK.................................................................................198
4.3.1. Electrical Sub-Block Requirements.........................................................198
4.3.2. Electrical Signal Specifications ..............................................................201
4.3.3. Differential Transmitter (Tx) Output Specifications...............................206
4.3.4. Differential Receiver (Rx) Input Specifications ......................................211
5. SOFTWARE INITIALIZATION AND CONFIGURATION ..........................215
5.1. CONFIGURATION TOPOLOGY............................................................................215
5.2. PCI E
XPRESS CONFIGURATION MECHANISMS..................................................216
5.2.1. PCI 2.3 Compatible Configuration Mechanism......................................217
5.2.2. PCI Express Enhanced Configuration Mechanism.................................218
5.2.3. Root Complex Register Block..................................................................218
5.3. C
ONFIGURATION TRANSACTION RULES ...........................................................219
5.3.1. Device Number........................................................................................219
5.3.2. Configuration Transaction Addressing...................................................219
5.3.3. Configuration Request Routing Rules.....................................................220
5.3.4. Generating PCI Special Cycles using PCI Configuration Mechanism #1
221
5.4. CONFIGURATION REGISTER TYPES...................................................................221
5.5. PCI-C
OMPATIBLE CONFIGURATION REGISTERS...............................................222
5.5.1. Type 0/1 Common Configuration Space .................................................223
5.5.2. Type 0 Configuration Space Header.......................................................228
5.5.3. Type 1 Configuration Space Header.......................................................229
5.6. PCI POWER MANAGEMENT CAPABILITY STRUCTURE......................................232
5.7. MSI C
APABILITY STRUCTURE..........................................................................234
5.8. PCI E
XPRESS CAPABILITY STRUCTURE............................................................234
5.8.1. PCI Express Capability List Register (Offset 00h) .................................235
5.8.2. PCI Express Capabilities Register (Offset 02h)......................................235
5.8.3. Device Capabilities Register (Offset 04h)...............................................237
5.8.4. Device Control Register (Offset 08h)......................................................241
5.8.5. Device Status Register (Offset 0Ah)........................................................244
5.8.6. Link Capabilities Register (Offset 0Ch)..................................................246
5.8.7. Link Control Register (Offset 10h)..........................................................248
5.8.8. Link Status Register (Offset 12h) ............................................................250
5.8.9. Slot Capabilities Register (Offset 14h)....................................................251
5.8.10. Slot Control Register (Offset 18h)...........................................................253
5.8.11. Slot Status Register (Offset 1Ah).............................................................255
5.8.12. Root Control Register (Offset 1Ch).........................................................256
5.8.13. Root Status Register (Offset 20h)............................................................257
5.9. PCI EXPRESS EXTENDED CAPABILITIES...........................................................258
5.9.1. Extended Capabilities in Configuration Space.......................................259
5.9.2. Extended Capabilities in the Root Complex Register Block ...................259
5.9.3. PCI Express Enhanced Capability Header.............................................259
5.10. ADVANCED ERROR REPORTING CAPABILITY ...............................................260
5.10.1. Advanced Error Reporting Enhanced Capability Header (Offset 00h)..261
5.10.2. Uncorrectable Error Status Register (Offset 04h)..................................262
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