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IA-PC HPET Specification Rev 1.0a 3
Table of Contents
1. IA-PC HPET........................................................................................................................................... 4
1.1 Revision History:............................................................................................................................ 4
1.2 Scope .............................................................................................................................................. 5
1.3 Terminology................................................................................................................................... 6
2. Hardware Overview................................................................................................................................ 7
2.1 Register Model Overview............................................................................................................... 8
2.1.1 Memory Map.......................................................................................................................... 8
2.2 Minimum Recommended Hardware Implementation .................................................................... 9
2.3 Register Definitions...................................................................................................................... 10
2.3.1 Register Overview................................................................................................................ 10
2.3.2 Programming Requirements................................................................................................. 10
2.3.3 Power Management Considerations ..................................................................................... 10
2.3.4 General Capabilities and ID Register ................................................................................... 11
General Capability and ID Register Addressing...................................................................................11
2.3.5 General Configuration Register............................................................................................ 12
2.3.6 General Interrupt Status Register.......................................................................................... 14
2.3.7 Main Counter Register.......................................................................................................... 15
2.3.8 Timer N Configuration and Capabilities Register ................................................................ 16
2.3.9 Timer N Comparator Register .............................................................................................. 19
2.3.9.1 Register Definition and Usage Model .............................................................................. 20
2.3.9.2 Periodic vs. Non-Periodic Modes..................................................................................... 21
2.3.9.2.1 Non-Periodic Mode.................................................................................................... 21
2.3.9.2.2 Periodic Mode............................................................................................................ 21
2.3.9.2.3 Read/Write Paths for Periodic Mode Vs One-Shot Mode ......................................... 22
2.3.10 Timer N FSB Interrupt Route Register................................................................................. 23
2.4 Theory Of Operation .................................................................................................................... 23
2.4.1 Timer Accuracy Rules.......................................................................................................... 23
2.4.2 Interrupt Mapping................................................................................................................. 24
2.4.2.1 Mapping Option #1: LegacyReplacement Option ........................................................... 24
2.4.2.2 Mapping Option #2: Standard Option ............................................................................. 24
2.4.2.3 Mapping Option #3: FSB Option..................................................................................... 24
2.4.3 Periodic vs. Non-Periodic Modes......................................................................................... 24
2.4.3.1 Non-Periodic Mode .......................................................................................................... 24
2.4.3.2 Periodic Mode...................................................................................................................25
2.4.4 Enabling the Timers.............................................................................................................. 25
2.4.5 Interrupt Levels..................................................................................................................... 25
2.4.6 Handling Interrupts............................................................................................................... 26
2.4.7 Issues related to 64-bit Timers with 32-bit CPUs................................................................. 26
3. Enumeration & Configuration of HPET............................................................................................... 27
3.1 Initial State of Event Timer Hardware.......................................................................................... 27
3.2 BIOS Initialization........................................................................................................................ 27
3.2.1 Assign memory to Timer Block(s) ....................................................................................... 27
3.2.2 HPET Block Interrupt Routing............................................................................................. 27
3.2.2.1 Routing Interrupts for HPET Blocks that do not support 8254/RTC IRQ Routing.......... 27
3.2.2.2 Routing Interrupts for HPET Blocks that support 8254/RTC IRQs ................................. 28
3.2.3 Considerations for Platforms without Legacy Timers.......................................................... 29
3.2.4 Create ACPI 2.0 HPET Description Table (HPET).............................................................. 30
3.2.5 Describe Event Timer(s) in ACPI Name space .................................................................... 32
3.2.5.1 ACPI Name Space Example............................................................................................. 32
3.2.6 Recommendations for OS Initialization code....................................................................... 32
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