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______________________________________________________________________________________
IA-PC HPET Specification Rev 1.0a 1
IA-PC HPET (High Precision Event Timers)
Specification
Revision: 1.0a
Date: October 2004
______________________________________________________________________________________
IA-PC HPET Specification Rev 1.0a 2
LEGAL DISCLAIMER
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-
INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY
OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
Intel disclaims all liability, including liability for infringement of any proprietary rights,
relating to use of information in this specification. No license, express or implied, by
estoppels or otherwise, to any intellectual property rights is granted herein.
This specification is a preliminary draft provided for comment and informational purposes
only, and is subject to change without any notice, obligation or liability. Readers should
not rely on this specification in any way for product design purposes.
It is Intel's intent to provide a Version 1.0 of this specification, that will be made available
subject to an appropriate license agreement. However, Intel is under no obligation or
liability to do so.
The contents of the areas marked as "reserved" in this specification will not be
licensed under the Intel license for this specification.
IA-PC HPET Specification
Copyright © 1999-2004 Intel Corporation
All rights reserved.
*T
HIRD-PARTY BRANDS AND NAMES MAY BE CLAIMED AS THE PROPERTY OF OTHERS.
______________________________________________________________________________________
IA-PC HPET Specification Rev 1.0a 3
Table of Contents
1. IA-PC HPET........................................................................................................................................... 4
1.1 Revision History:............................................................................................................................ 4
1.2 Scope .............................................................................................................................................. 5
1.3 Terminology................................................................................................................................... 6
2. Hardware Overview................................................................................................................................ 7
2.1 Register Model Overview............................................................................................................... 8
2.1.1 Memory Map.......................................................................................................................... 8
2.2 Minimum Recommended Hardware Implementation .................................................................... 9
2.3 Register Definitions...................................................................................................................... 10
2.3.1 Register Overview................................................................................................................ 10
2.3.2 Programming Requirements................................................................................................. 10
2.3.3 Power Management Considerations ..................................................................................... 10
2.3.4 General Capabilities and ID Register ................................................................................... 11
General Capability and ID Register Addressing...................................................................................11
2.3.5 General Configuration Register............................................................................................ 12
2.3.6 General Interrupt Status Register.......................................................................................... 14
2.3.7 Main Counter Register.......................................................................................................... 15
2.3.8 Timer N Configuration and Capabilities Register ................................................................ 16
2.3.9 Timer N Comparator Register .............................................................................................. 19
2.3.9.1 Register Definition and Usage Model .............................................................................. 20
2.3.9.2 Periodic vs. Non-Periodic Modes..................................................................................... 21
2.3.9.2.1 Non-Periodic Mode.................................................................................................... 21
2.3.9.2.2 Periodic Mode............................................................................................................ 21
2.3.9.2.3 Read/Write Paths for Periodic Mode Vs One-Shot Mode ......................................... 22
2.3.10 Timer N FSB Interrupt Route Register................................................................................. 23
2.4 Theory Of Operation .................................................................................................................... 23
2.4.1 Timer Accuracy Rules.......................................................................................................... 23
2.4.2 Interrupt Mapping................................................................................................................. 24
2.4.2.1 Mapping Option #1: LegacyReplacement Option ........................................................... 24
2.4.2.2 Mapping Option #2: Standard Option ............................................................................. 24
2.4.2.3 Mapping Option #3: FSB Option..................................................................................... 24
2.4.3 Periodic vs. Non-Periodic Modes......................................................................................... 24
2.4.3.1 Non-Periodic Mode .......................................................................................................... 24
2.4.3.2 Periodic Mode...................................................................................................................25
2.4.4 Enabling the Timers.............................................................................................................. 25
2.4.5 Interrupt Levels..................................................................................................................... 25
2.4.6 Handling Interrupts............................................................................................................... 26
2.4.7 Issues related to 64-bit Timers with 32-bit CPUs................................................................. 26
3. Enumeration & Configuration of HPET............................................................................................... 27
3.1 Initial State of Event Timer Hardware.......................................................................................... 27
3.2 BIOS Initialization........................................................................................................................ 27
3.2.1 Assign memory to Timer Block(s) ....................................................................................... 27
3.2.2 HPET Block Interrupt Routing............................................................................................. 27
3.2.2.1 Routing Interrupts for HPET Blocks that do not support 8254/RTC IRQ Routing.......... 27
3.2.2.2 Routing Interrupts for HPET Blocks that support 8254/RTC IRQs ................................. 28
3.2.3 Considerations for Platforms without Legacy Timers.......................................................... 29
3.2.4 Create ACPI 2.0 HPET Description Table (HPET).............................................................. 30
3.2.5 Describe Event Timer(s) in ACPI Name space .................................................................... 32
3.2.5.1 ACPI Name Space Example............................................................................................. 32
3.2.6 Recommendations for OS Initialization code....................................................................... 32
______________________________________________________________________________________
IA-PC HPET Specification Rev 1.0a 4
1. IA-PC HPET
1.1 Revision History:
Version Comments
0.97 Last Updated: 03/07/2000
• Incorporated technical editing changes, released for external feedback.
0.97a Last Updated: 05/18/2000
• Incorporated various non-technical and legal feedbacks.
0.98 01/20/2002
• Product name changed: from Multimedia Timer to HPET (High Precision Event Timer)
• Technologic term changed: from Legacy Mode to LegacyReplacement Mode for clarity purpose
• ETDT ACPI table changed: ETDT (Event Timer Descriptor Table) is changed to HPET table and its content of the table
has been updated.
• IA64 platform support: Use GAS(Generic Address Structure) format in HPET table and up to 64KB timer block.
0.98a 08/31/2001
• Modified the accuracy of clock frequency drift to 0.05%
• Add “write lock” note to the programming requirement
1.0 6/8/2004
• Removed color-code for read-only fields
• Added programming notes for 64-bit register access in a 64-bit platform
• Explicitly mark “Reserved” in reserved fields of FSB Registers
1.0a 6/8/2004
• Clarifications to 64 bit accesses.
• General cleanup
______________________________________________________________________________________
IA-PC HPET Specification Rev 1.0a 5
1.2 Scope
This specification provides register model and programming interface definitions for new event timer
hardware for use on Intel Architecture-based Personal Computers. In this specification, the terms ‘IA-PC
HPET and ‘Event Timers’ refer to the same timer hardware.
The IA-PC HPET Specification defines timer hardware that is intended to initially supplement and
eventually replace the legacy 8254 Programmable Interval Timer and the Real Time Clock Periodic
Interrupt generation functions that are currently used as the ‘de-facto’ timer hardware for IA-PCs.
This new timer hardware can be used by system software for:
• Synchronizing
o Real-Time Digital Audio & Video Streams
64-bit free running up-counter
• Scheduling
o Threads, Tasks, Processes, etc.
Fixed Rate (Periodic) Interrupt Generation
• System Heart Beat
• Non-Real Time Thread Scheduler
Variable Rate (One-Shot) Interrupt Generation
• Scheduling real time tasks associated with host-based signal processing
applications
• Time Stamping
o On Multiprocessor platforms
64-Bit free running up-counter can be utilized as DIG64 “platform timer” for
Time Stamping Applications. This provides a time-base that is insensitive to
clock frequency drifts on individual CPU’s on a N-Way MP systems.
Note:
The name of the timer block has been changed from Multimedia Timer to HPET (High Precision
Event Timer). However, before the new name was adopted, many related documents continue to use
or reference the term of “Multimedia Timer”. Therefore, for the purposes of designing products to
this specification, the terms HPET, Multimedia Timer, MMT and MM Timer should be treated as
the same timer hardware.
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