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Version 1.5.1 April 2009
Copyright © PLDA 1996-2009
AHB-PCI Express Bridge IP Core
Reference Manual
AHB-PCIe Bridge Reference Manual
2
AHB-PCIe Bridge
Reference Manual
Documentation Change History
Date Version Number Changes
April 2009 1.5.1
• k_bridge[6] signal now reserved.
• PHY interface now compliant with Intel PIPE 2.00 Specification.
March 2009 1.5.0
• Added explanation for how to implement dual mode using Core
Customisation parameters.
October 2008 1.5.0
• Added support for AHB throughput optimization.
August 2008 1.4.0
• Added support for 2.5/5.0 Gbps link speed
• Updated memory and logic specifications
March 2008 1.3.5
• No documentation changes
January 2008 1.3.4
• lCorrected reset connections diagrams
November 2007 1.3.3
• Added AHB big-endian support with k_bridge(7)
• Updated memory usage table
August 2007 1.3.2
• Changes to PCIExpress reset signals
• Changes to k_bridge signal
• Added “turn off link” bit to ICMD register
• Changed “assert” CLKREQ# signal and ICMD bit to “deassert“
June 2007 1.3.1
• Corrected interrupt mask & status registers layout
April 2007 1.3
• Added root-port mode & related registers
• Removed AHB-PCI post error interrupt
• Added PCI-AHB write doorbell interrupt
• Changes to k_bridge signal
• Added core logic usage
• Added more information on reset scheme
March 2007 1.2
• Added ASPM and ExpressCard features
• Updated memory buffer size information
• Changes to k_bridge & k_fix signals
February 2007 1.1
• New registers, functionalities and signals described
• General clean-up of documentation
January 2007 1.0 Rev 2
• k_bridge now includes 16 bits instead of 1
• Updated description of k_pciahb[63:0]
November 2006 1.0 Rev 1
• Added description for k_pciconf[127:0]
October 2006 1.0
• First release
3
AHB-PCIe Bridge Reference Manual
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks owned by PLDA SA. Other brands
and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars
of the product and its use contained in this document are given by PLDA in good faith. This document is provided
“as is” with no warranties whatsoever, including any warranty of merchantability, non infringement, fitness for any
particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
This document is intended only to assist the reader in the use of the product. PLDA shall not be liable for any loss
or damage arising from the use of any information in this document, or any error or omission in such information,
or any incorrect use of the product. Nor shall PLDA be liable for infringement of proprietary rights relating to use of
information in this document. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein.
Product Status
The information in this document is final content pertaining to the PLDA AHB-PCI Express Bridge IP Core.
Web Address
http://www.plda.com
AHB-PCIe Bridge Reference Manual
4
Table of Contents
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Feedback and Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.1 General Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Clocks & Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Memory & Logic Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 2 AHB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 AHB Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.1 Slave Interface Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.2 Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Bridge Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 PCI Express Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.1 PCI Control & Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.2 Bridge Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.3 PCI Legacy Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.4 Active State Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 AHB-PCI window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5.1 AHB Discard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5.2 Transaction Forwarding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6 Processor Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6.1 Endpoint PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6.2 Rootport PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6.3 DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6.4 Endpoint Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6.5 Rootport Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6.6 AHB-PCI Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
AHB-PCIe Bridge Reference Manual
2.6.7 PCI-AHB Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7 DMA Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.1 DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7.2 DMA Byte Boundary with Shifting Capabilities (Burst Mode) . . . . . . . . . . . . . . . . . . . . . . 25
2.7.2.1 Example 1: Write DMA Alignment (AHB Read, PCI Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.7.2.2 Example 2: Read DMA Alignment (PCI Read, AHB Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Chapter 3 AHB - PCIe Bridge Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.1 AHB Slave Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 AHB Master Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 PCI Express Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 4 PCI Express Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 PCI Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.1 PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.2 Type 0 Configuration Settings (endpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.3 Type 1 Configuration Settings (rootport) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.4 MSI Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.5 AER Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.6 Power Management Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.7 PCI Express Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3 PCI-AHB Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.1 PCI-AHB Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.2 Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.3 Transaction Forwarding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 5 Core Customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
剩余41页未读,继续阅读
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