Virtex-5 FPGA User Guide www.xilinx.com UG190 (v4.2) May 9, 2008
09/11/07 3.1 Chapter 1: Added “Clock Gating for Power Savings” on page 22. Revised Figure 1-2, page 26.
Revised Figure 1-16, page 33.
Chapter 2: Revised DCM reset and locking process in “Reset Input - RST,” page 49. Updated
DO[2] description in Table 2-4, page 52. Changed the multiply value range on page 54.
Revised the description for “FACTORY_JF Attribute,” page 57. Revised “Output Clocks,”
page 61, updated Figure 2-7, page 70, and added a BUFG to Figure 2-10, page 72. Added more
steps to Dynamic Reconfiguration (DRPs) when loading new M and D values on page 68.
Updated Figure 2-7, page 70. Revised bulleted descriptions under Figure 2-20, page 83.
Chapter 3: Updated Figure 3-1, page 86. Add notes to Table 3-2, page 90. Added a note to
“Phase Shift,” page 92. Added rounding to Equation 3-3 through Equation 3-6. Revised
CLKFBIN, CLKFBDCM, CLKFBOUT, RST, LOCKED, and added the REL pin and note 2 to
Table 3-3, page 93. Added RESET_ON_LOSS_OF_LOCK attribute to Table 3-4, page 95.
Removed general routing discussion from “PLL Clock Input Signals.”Revised “Missing Input
Clock or Feedback Clock” section. Added waveforms to Figure 3-13. Corrected the Virtex-4
port mapping in Figure 3-17 and Table 3-8, page 108.
Chapter 4: Revised and clarified “Built-in Error Correction.” Edited WE signal throughout.
Clarified Readback limitation in “Simple Dual-Port Block RAM” on page 119. Edited
“Set/Reset - SSR[A|B],” page 123. Added “Block RAM Retargeting,” page 138. Revised
latency values and added Note 1 to Table 4-16, page 144. Updated “Cascading FIFOs to
Increase Depth,” page 156.
Chapter 5: Clarified information about common control signals in a slice in “Storage
Elements” on page 176.
Chapter 6: Updated the DCI cascading guidelines on page 221. Removed references to
“HSLVDCI Controlled Impedance Driver with Unidirectional Termination” since it is not
supported in software. Added note 3 to Table 6-17, page 254. Clarified the introduction to
“SSTL (Stub-Series Terminated Logic),” page 272. Revised “DIFF_SSTL2_II_DCI,
DIFF_SSTL18_II_DCI” on page 273. Fixed DIFF_SSTL2_II references in Figure 6-73, page 280.
Revised rules 2 and 3 in “Rules for Combining I/O Standards in the Same Bank,” page 296.
Deleted of absolute maximum table from “Overshoot/Undershoot,” page 300.
Chapter 7: Removed DDLY port from IDDR primitive page 319. Added the SIGNAL
_PATTERN, DELAY_SRC, and REFCLK_FREQUENCY attributes to Table 7-10, page 327.
Revised Figure 7-9, page 329. Removed Table 7-12: “Generating Reference Clock From DCM”
and updated REFCLK section in “IDELAYCTRL Ports” on page 337. Clarified introduction in
“IDELAYCTRL Locations,” page 338. Changed ODDR “Clock Forwarding,” page 346.
Chapter 8: Updated SR and O in Figure 8-2 and Table 8-1, page 355. Updated the entire
section for “BITSLIP Submodule,” page 366. Fixed typographical errors in Figure 8-14,
page 370.
12/11/07 3.2 Chapter 1: Revised description in “Clock Gating for Power Savings,” page 22. Added the
XC5VLX20T, XC5VLX155, and XC5VLX155T devices to Table 1-5.
Chapter 2: Added the XC5VLX20T, XC5VLX155, and XC5VLX155T devices to Table 2-1.
Chapter 3: Revised “Clock Network Deskew,” page 90. Removed note 2 and revised
descriptions of CLKFBOUT and DEN in Table 3-3, page 93. Revised allowed value of
CLKOUT[0:5]_PHASE and CLKFBOUT_MULT description in Table 3-4, page 95. Revised
Figure 3-13 and Figure 3-14 including waveforms.
Chapter 5: Added the XC5VLX20T, XC5VLX155, and XC5VLX155T devices to Table 5-2.
Chapter 6: Clarified discussion of cascading across CMT tiles in “DCI Cascading.” Changed
the split termination to V
TT
=0.9V in Figure 6-83, page 290.
Chapter 7: Added to the descriptions of the “HIGH_PERFORMANCE_MODE Attribute,”
and the “SIGNAL_PATTERN Attribute,” page 328 including Table 7-10. Revised description
in “Instantiating IDELAYCTRL Without LOC Constraints,” page 339.
Chapter 8: Complete rewrite of the chapter. Many changes to descriptions, tables, and figures.
Date Version Revision
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