MT53B256M32D1NP.pdf

需积分: 50 909 浏览量更新于2023-03-03 评论收藏 3.99MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源评论

资源推荐

Mobile LPDDR4 SDRAM

MT53B256M32D1, MT53B512M32D2, MT53B1024M32D4

Features

• Ultra-low-voltage core and I/O power supplies

–V

DD1

= 1.70–1.95V; 1.8V nominal

–V

DD2

DDQ

= 1.06–1.17V; 1.10V nominal

• Frequency range

– 1600–10 MHz (data rate range: 3200–20 Mb/s/

pin)

•16n prefetch DDR architecture

• 2-channel partitioned architecture for low RD/WR

energy and low average latency

• 8 internal banks per channel for concurrent opera-

tion

• Single-data-rate CMD/ADR entry

• Bidirectional/differential data strobe per byte lane

• Programmable READ and WRITE latencies (RL/WL)

• Programmable and on-the-fly burst lengths (BL =

16, 32)

• Directed per-bank refresh for concurrent bank op-

eration and ease of command scheduling

• Up to 12.8 GB/s per die (2 channels x 6.4 GB/s)

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Selectable output drive strength (DS)

• Clock-stop capability

• RoHS-compliant, “green” packaging

• Programmable V

SSQ

(ODT) termination

Options Marking

•V

DD1

DD2

: 1.8V/1.1V B

• Array configuration

– 256 Meg x 32 (2 channels x16 I/O) 256M32

– 512 Meg x 32 (2 channels x16 I/O) 512M32

– 1024 Meg x 32 (2 channels x8 I/O x 2) 1024M32

• Device configuration

– 256M16 x 2 channel x 1 die D1

– 256M16 x 2 channel x 2 die D2

– 512M8 x 2 channel x 4 die D4

• FBGA “green” package

– 200-ball WFBGA (10mm x 14.5mm x

0.80mm)

– 200-ball VFBGA (10mm x 14.5mm x

0.95mm)

• Speed grade, cycle time -062

– 625ps @ RL = 28/32 (x16 device)

– 625ps @ RL = 32/36 (x8 device)

• Operating temperature range

– –30°C to +85°C WT

• Revision :C

Table 1: Key Timing Parameters

Speed

Grade

Array

configura-

tion

Device

Type

Clock Rate

(MHz)

Data Rate

(Mb/s/pin)

WRITE Latency READ Latency

Set A Set B

DBI

Disabled

DBI

Enabled

-062 256Mb x 32

512Mb x 32

x16 device 1600 3200 14 26 28 32

1024Mb x 32 x8 device 1600 3200 14 26 32 36

Micron Confidential and Proprietary Preliminary

‡

200b: x32 Mobile LPDDR4 SDRAM

Features

PDF: 09005aef8653a92d

200b_z01m_sdp_ddp_qdp_mobile_lpddr4.pdf – Rev. B 4/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.

Contents

General Description ....................................................................................................................................... 17

General Notes ............................................................................................................................................ 17

Package Block Diagrams ................................................................................................................................. 18

Ball Assignments and Descriptions ................................................................................................................. 21

Package Dimensions ....................................................................................................................................... 23

MR0, MR[6:3], MR8, MR13 Readout ................................................................................................................. 25

Parameters ............................................................................................................................................... 26

Functional Description ................................................................................................................................... 28

Monolithic Device Addressing ......................................................................................................................... 28

Simplified Bus Interface State Diagram ............................................................................................................ 32

Power-Up and Initialization ............................................................................................................................ 33

Voltage Ramp ............................................................................................................................................. 34

Reset Initialization with Stable Power .......................................................................................................... 36

Power-Off Sequence ....................................................................................................................................... 37

Controlled Power-Off .................................................................................................................................. 37

Uncontrolled Power-Off .............................................................................................................................. 37

Mode Registers ............................................................................................................................................... 38

Mode Register Assignments and Definitions ................................................................................................ 38

Commands and Timing .................................................................................................................................. 64

Truth Tables ................................................................................................................................................... 64

ACTIVATE Command ..................................................................................................................................... 67

Read and Write Access Modes ......................................................................................................................... 68

Preamble and Postamble ................................................................................................................................ 69

Burst READ Operation .................................................................................................................................... 72

Read Timing ............................................................................................................................................... 74

LZ(DQS),

LZ(DQ),

HZ(DQS),

HZ(DQ) Calculation ..................................................................................... 74

LZ(DQS) and

HZ(DQS) Calculation for ATE (Automatic Test Equipment) .................................................... 75

LZ(DQ) and

HZ(DQ) Calculation for ATE (Automatic Test Equipment) ........................................................ 76

Burst WRITE Operation .................................................................................................................................. 78

Write Timing .............................................................................................................................................. 80

WPRE Calculation for ATE (Automatic Test Equipment) .............................................................................. 81

WPST Calculation for ATE (Automatic Test Equipment) ............................................................................... 81

MASK WRITE Operation ................................................................................................................................. 82

Mask Write Timing Constraints for BL16 ...................................................................................................... 84

Data Mask and Data Bus Inversion (DBI[DC]) Function ................................................................................... 86

Preamble and Postamble Behavior .................................................................................................................. 90

Preamble, Postamble Behavior in READ-To-READ Operations ...................................................................... 90

READ to READ Operations – Seamless ......................................................................................................... 90

READ to READ Operations – Consecutive .................................................................................................... 91

Write to Write Operations – Seamless .......................................................................................................... 98

Write to Write Operations – Consecutive ..................................................................................................... 101

PRECHARGE Operation ................................................................................................................................. 105

Burst Read Operation Followed by Precharge .............................................................................................. 105

Burst Write Followed by Precharge ............................................................................................................. 106

Auto Precharge .............................................................................................................................................. 107

Burst READ With Auto Precharge ............................................................................................................... 107

Burst WRITE With Auto Precharge .............................................................................................................. 108

RAS Lock Function .................................................................................................................................... 112

Delay time from Write to Read with Auto Precharge .................................................................................... 113

REFRESH Command ..................................................................................................................................... 114

Micron Confidential and Proprietary Preliminary

200b: x32 Mobile LPDDR4 SDRAM

Part Number Ordering Information

PDF: 09005aef8653a92d

200b_z01m_sdp_ddp_qdp_mobile_lpddr4.pdf – Rev. B 4/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Refresh Requirement ..................................................................................................................................... 119

SELF REFRESH Operation .............................................................................................................................. 120

Self Refresh Entry and Exit ......................................................................................................................... 120

Power-Down Entry and Exit During Self Refresh ......................................................................................... 121

Command Input Timing After Power Down Exit .......................................................................................... 122

Self Refresh Abort ...................................................................................................................................... 123

MRR, MRW, MPC Command During

XSR,

RFC .......................................................................................... 123

Power-Down Mode ........................................................................................................................................ 126

Power-Down Entry and Exit ....................................................................................................................... 126

Input Clock Stop and Frequency Change ........................................................................................................ 136

Clock Frequency Change – CKE LOW ......................................................................................................... 136

Clock Stop – CKE LOW ............................................................................................................................... 136

Clock Frequency Change – CKE HIGH ........................................................................................................ 136

Clock Stop – CKE HIGH ............................................................................................................................. 137

MODE REGISTER READ Operation ................................................................................................................ 138

MRR after Read and Write Command ......................................................................................................... 139

MRR after Power-Down Exit ....................................................................................................................... 141

MODE REGISTER WRITE ............................................................................................................................... 142

Mode Register Write States ......................................................................................................................... 142

REF

Current Generator (VRCG) ..................................................................................................................... 144

REF

Training ................................................................................................................................................. 146

REF(CA)

Training ........................................................................................................................................ 146

REF(DQ)

Training ....................................................................................................................................... 151

Command Bus Training ................................................................................................................................. 156

Command Bus Training Mode .................................................................................................................... 156

Training Sequence for Single-Rank Systems ................................................................................................ 157

Training Sequence for Multiple-Rank Systems ............................................................................................ 158

Relation between CA Input pin DQ Output pin ........................................................................................... 159

Write Leveling ............................................................................................................................................... 163

Mode Register Write-WR Leveling Mode ..................................................................................................... 163

Write-Leveling Procedure: .......................................................................................................................... 163

Input Clock Frequency Stop and Change .................................................................................................... 164

MULTIPURPOSE Operation ........................................................................................................................... 167

Read DQ Calibration Training ........................................................................................................................ 172

Read DQ Calibration Procedure ................................................................................................................. 172

DQ Read Training Example ........................................................................................................................ 174

MPC of Read DQ Calibration after Power-Down Exit ................................................................................... 175

Write Training ............................................................................................................................................... 176

Internal Interval Timer .............................................................................................................................. 181

DQS Interval Oscillator Matching Error ...................................................................................................... 183

OSC Count Readout Time .......................................................................................................................... 184

Thermal Offset .............................................................................................................................................. 186

Temperature Sensor ...................................................................................................................................... 186

ZQ Calibration ............................................................................................................................................... 187

ZQCAL Reset ............................................................................................................................................. 188

Multichannel Considerations ..................................................................................................................... 189

ZQ External Resistor, Tolerance, and Capacitive Loading ............................................................................. 189

Frequency Set Points ..................................................................................................................................... 190

Frequency set point update Timing ............................................................................................................ 191

Pull-Up and Pull-Down Characteristics and Calibration .................................................................................. 195

On-Die Termination for the Command/Address Bus ....................................................................................... 196

ODT Mode Register and ODT State Table .................................................................................................... 196

Micron Confidential and Proprietary Preliminary

200b: x32 Mobile LPDDR4 SDRAM

Part Number Ordering Information

PDF: 09005aef8653a92d

200b_z01m_sdp_ddp_qdp_mobile_lpddr4.pdf – Rev. B 4/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.