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Contents
A40i User Manual(Revision 1.1) Copyright© 2018 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 17
3.18.6.69. PH Multi-Driving Register 0(Default Value: 0x5555_5555) ...................................................... 374
3.18.6.70. PH Multi-Driving Register 1(Default Value: 0x0055_5555) ...................................................... 374
3.18.6.71. PH Pull Register 0(Default Value: 0x0000_0000) ..................................................................... 374
3.18.6.72. PH Pull Register 1(Default Value: 0x0000_0000)...................................................................... 374
3.18.6.73. PI Configure Register 0(Default Value: 0x7777_7777) ............................................................. 375
3.18.6.74. PI Configure Register 1(Default Value: 0x7777_7777) ............................................................. 376
3.18.6.75. PI Configure Register 2(Default Value: 0x0077_7777) ............................................................. 377
3.18.6.76. PI Configure Register 3(Default Value: 0x0000_0000) ............................................................. 378
3.18.6.77. PI Data Register(Default Value: 0x0000_0000) ........................................................................ 378
3.18.6.78. PI Multi-Driving Register 0(Default Value: 0x5555_5555) ....................................................... 378
3.18.6.79. PI Multi-Driving Register 1(Default Value: 0x0000_0555) ....................................................... 379
3.18.6.80. PI Pull Register 0(Default Value: 0x0000_0000) ....................................................................... 379
3.18.6.81. PI Pull Register 1(Default Value: 0x0000_0000) ....................................................................... 379
3.18.6.82. PIO Interrupt Configure Register 0(Default Value: 0x0000_0000) ........................................... 379
3.18.6.83. PIO Interrupt Configure Register 1(Default Value: 0x0000_0000) ........................................... 380
3.18.6.84. PIO Interrupt Configure Register 2(Default Value: 0x0000_0000) ........................................... 380
3.18.6.85. PIO Interrupt Configure Register 3(Default Value: 0x0000_0000) ........................................... 380
3.18.6.86. PIO Interrupt Control Register(Default Value: 0x0000_0000) .................................................. 381
3.18.6.87. PIO Interrupt Status Register(Default Value: 0x0000_0000) .................................................... 381
3.18.6.88. PIO Interrupt Debounce Register(Default Value: 0x0000_0000) ............................................. 381
Chapter 4. Memory ........................................................................................................................................................... 382
4.1. DRAMC ............................................................................................................................................................... 383
4.1.1. Overview ................................................................................................................................................. 383
4.2. NAND Flash Controller(NDFC) ............................................................................................................................ 384
4.2.1. Overview ................................................................................................................................................. 384
4.2.2. Block Diagram ......................................................................................................................................... 384
4.2.3. Operations and Functional Descriptions ................................................................................................. 385
4.2.3.1. External Signals ............................................................................................................................ 385
4.2.3.2. Clock Sources................................................................................................................................ 386
4.2.3.3. NDFC Timing Diagram .................................................................................................................. 386
4.2.3.4. NDFC Operation Guide ................................................................................................................. 390
4.2.4. Programming Guidelines ......................................................................................................................... 392
4.2.4.1. Initializing Nand Flash ..................................................................................................................
392
4.2.4.2. Erasing Nand Flash ....................................................................................................................... 392
4.2.4.3. Writing Nand Flash ....................................................................................................................... 393
4.2.4.4. Reading Nand Flash ...................................................................................................................... 393
4.2.5. Register List ............................................................................................................................................. 393
4.2.6. Register Description ................................................................................................................................ 394
4.2.6.1. NDFC Control Register(Default Value: 0x0000_0000) .................................................................. 394
4.2.6.2. NDFC Status Register(Default Value: 0x0000_0000) .................................................................... 396
4.2.6.3. NDFC Interrupt and DMA Enable Register(Default Value: 0x0000_0000) ................................... 397
4.2.6.4. NDFC Timing Control Register(Default Value: 0x0000_0000) ...................................................... 397
4.2.6.5. NDFC Timing Configure Register(Default Value: 0x0000_0095) .................................................. 398
4.2.6.6. NDFC Address Low Word Register(Default Value: 0x0000_0000) ................................................ 399
4.2.6.7. NDFC Address High Word Register(Default Value: 0x0000_0000) ............................................... 399
4.2.6.8. NDFC Data Block Number Register(Default Value: 0x0000_0000) .............................................. 400
4.2.6.9. NDFC Data Counter Register(Default Value: 0x0000_0000) ........................................................ 400
4.2.6.10. NDFC Command IO Register(Default Value: 0x0000_0000) ...................................................... 400
4.2.6.11. NDFC Command Set Register 0(Default Value: 0x00E0_0530) .................................................. 402
4.2.6.12. NDFC Command Set Register 1(Default Value: 0x7000_8510) .................................................. 402
4.2.6.13. NDFC ECC Control Register(Default Value: 0x4A80_0008) ........................................................ 402
4.2.6.14. NDFC ECC Status Register(Default Value: 0x0000_0000) ........................................................... 403
4.2.6.15. NDFC Enhanced Feature Register(Default Value: 0x0000_0000) ............................................... 404
4.2.6.16. NDFC Error Counter Register 0(Default Value: 0x0000_0000) ................................................... 404
4.2.6.17. NDFC Error Counter Register 1(Default Value: 0x0000_0000) ................................................... 404
4.2.6.18. NDFC Error Counter Register 2(Default Value: 0x00000000) ..................................................... 405