BCM54213PE: 千兆以太网PHY芯片技术规格

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"BCM54213PEB1KMLG是博通公司的一款千兆PHY芯片，适用于RGMII接口，支持10/100/1000BASE-T以太网速度，集成多种物理层功能，提供高集成度的解决方案，确保在标准Cat5 UTP线缆上的稳定运行。" 博通千兆PHY应用手册中的BCM54213PE是一款高度集成的单端口10/100/1000BASE-T Gigabit Ethernet（吉比特以太网）收发器。这款芯片采用三速设计，能够支持千兆、百兆及十兆的以太网通信。其特色在于它能够在标准的Category 5非屏蔽双绞线（UTP）上实现10BASE-T的运行，并且兼容Category 3、4和5线缆。 BCM54213PE包含了多种关键组件，如数字自适应均衡器、模数转换器（ADCs）、锁相环（PLLs）、线路驱动器、编码器、解码器、回声消除器和串扰消除器，以及所有必要的辅助电路。这些组件确保了设备在物理层的所有功能得以顺利执行。此外，该芯片基于博通成熟的数字信号处理技术，旨在与RGMII（ Reduced Gigabit Media Independent Interface）标准完全兼容，这使得它可以与业界标准的以太网MAC（媒体访问控制器）和交换机控制器无缝对接。为了确保在最恶劣环境下的可靠运行，BCM54213PE具备自动协商功能，能与其链接伙伴进行协商，以确定最佳的连接速度和工作模式。这种芯片的自动协商能力对于网络连接的稳定性和适应性至关重要，它能够适应不同的网络环境，确保数据传输的高效和可靠。在实际应用中，BCM54213PE通常用于网络设备如路由器、交换机或网络接口卡（NIC）中，以提供高速的以太网连接。其RGMII接口简化了系统设计，降低了外部组件的需求，从而降低了整体成本。同时，其在标准线缆上的兼容性也增加了设计的灵活性，使其能在各种网络基础设施中广泛使用。总结来说，BCM54213PE是一款高性能、高集成度的千兆以太网PHY芯片，适用于需要高速网络连接的各类应用场景，特别适合那些要求低功耗、小尺寸和高可靠性的网络设备设计。

Table of ContentsBCM54213PE Data Sheet

Broadcom

November 23, 2015 • 54213PE-DS102-R Page 16

BROADCOM CONFIDENTIAL

Section 5: Timing and AC Characteristics .................................................................... 149

REFCLK Input Timing .............................................................................................................................. 150

Section 6: Electrical Characteristics ............................................................................. 154

Section 7: Mechanical and Thermal............................................................................... 157

ROHS-Compliant Packaging ................................................................................................................... 157

Mechanical Information ........................................................................................................................... 158

Thermal Information................................................................................................................................. 159

Section 8: Ordering Information .................................................................................... 160

Appendix A: Acronyms and Abbreviations .................................................................. 161

List of FiguresBCM54213PE Data Sheet

Broadcom

November 23, 2015 • 54213PE-DS102-R Page 17

BROADCOM CONFIDENTIAL

List of Figures

Figure 1: Functional Block Diagram................................................................................................................... 2

Figure 2: Typical RGMII-to-10/100/1000BASE-T Application .......................................................................... 25

Figure 3: Typical RGMII-to-100BASE-EFX Fiber Application .......................................................................... 25

Figure 4: Native EEE Mode (MAC-Supported EEE LPI).................................................................................. 37

Figure 5: AutogrEEEn Mode (PHY-Supported EEE LPI)................................................................................. 39

Figure 6: BCM54213PE 36-Pin QFN Pinout Diagram, Top View .................................................................... 47

Figure 7: Internal Loopback Mode ................................................................................................................... 51

Figure 8: Line-Side (Remote) Loopback Mode ................................................................................................ 52

Figure 9: External Loopback Mode .................................................................................................................. 52

Figure 10: LED Circuit for Dual Input Configuration/LED Output Pins............................................................. 57

Figure 11: Programmable LED Multiplexer...................................................................................................... 58

Figure 12: Reset Timing................................................................................................................................. 149

Figure 13: REFCLK Input Timing................................................................................................................... 150

Figure 14: Management Interface Timing ...................................................................................................... 151

Figure 15: RGMII Input Timing (Normal Mode): GTXCLK and TXD[3:0] ....................................................... 151

Figure 16: RGMII Input Timing (Delayed Mode): GTXCLK and TXD[3:0] ..................................................... 152

Figure 17: RGMII Output Timing (Normal Mode): RXC and RXD[3:0]........................................................... 152

Figure 18: RGMII Output Timing (Delayed Mode): RXC and RXD[3:0] ......................................................... 153

Figure 19: 36-Pin QFN Package.................................................................................................................... 158

List of TablesBCM54213PE Data Sheet

BROADCOM CONFIDENTIAL

Broadcom

November 23, 2015 • 54213PE-DS102-R Page 18

List of Tables

Table 1: RGMII Mode Selection by Software ................................................................................................... 24

Table 2: Changing the Number of Failed Link Attempts before Downgrade.................................................... 34

Table 3: EEE Timing Parameters .................................................................................................................... 41

Table 4: Hardware Signal Descriptions............................................................................................................ 43

Table 5: 1000BASE-T External Loopback With External Loopback Plug ........................................................ 52

Table 6: 1000BASE-T External Loopback Without External Loopback Plug ................................................... 53

Table 7: 100BASE-TX External Loopback With External Loopback Plug........................................................ 53

Table 8: 100BASE-TX External Loopback Without External Loopback Plug................................................... 53

Table 9: 10BASE-TX External Loopback With External Loopback Plug.......................................................... 53

Table 10: 10BASE-T External Loopback Without External Loopback Plug ..................................................... 53

Table 11: RGMII Transmit Data ....................................................................................................................... 55

Table 12: RGMII Receive Data ........................................................................................................................ 55

Table 13: Dual Input Configuration/LED Outputs............................................................................................. 57

Table 14: Programmable LEDs........................................................................................................................ 58

Table 15: LINKSPD[2:1] LED Function (Default-LED Mode/Non-LOM-LED Mode) ........................................ 59

Table 16: LED Modes ...................................................................................................................................... 60

Table 17: MII Management Frame Format ...................................................................................................... 64

Table 18: Register Map.................................................................................................................................... 66

Table 19: 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Address 00h) ................................... 69

Table 20: 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (Address 01h) .................................... 72

Table 21: 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (Addresses 02h and 03h)............. 75

Table 22: 1000BASE-T/100BASE-TX/10BASE-T Auto-Negotiation Advertisement Register

(Address 04h) ................................................................................................................................. 75

Table 23: 1000BASE-T/100BASE-TX/10BASE-T Auto-Negotiation Link Partner Ability Register

(Address 05h) ................................................................................................................................. 78

Table 24: 1000BASE-T/100BASE-TX/10BASE-T Auto-Negotiation Expansion Register (Address 06h) ........ 80

Table 25: 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (Address 07h) ..................... 81

Table 26: 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page Register

(Address 08h) ................................................................................................................................. 82

Table 27: 1000BASE-T Control Register (Address 09h) ................................................................................. 83

Table 28: 1000BASE-T Status Register (Address 0Ah) .................................................................................. 85

Table 29: 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (Address 0Fh)................. 86

Table 30: 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (Address 10h) ................ 87

Table 31: 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (Address 11h).................. 89

Table 32: 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (Address 12h) ................. 92

Table 33: 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter Register (Address 13h) ....... 93

List of TablesBCM54213PE Data Sheet

BROADCOM CONFIDENTIAL

Broadcom

November 23, 2015 • 54213PE-DS102-R Page 19

Table 34: 1000BASE-T/100BASE-TX/10BASE-T Receiver NOT_OK Counter Register (Address 14h) ......... 93

Table 35: 1000BASE-T/100BASE-TX/10BASE-T Expansion Register Access Register (Address 17h) ......... 93

Table 36: Expansion Register Select Values................................................................................................... 94

Table 37: 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Shadow Values Access .......................... 94

Table 38: Reading Register 18h ...................................................................................................................... 95

Table 39: Writing Register 18h ........................................................................................................................ 95

Table 40: 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Register

(Address 18h, Shadow Value 000) .................................................................................................96

Table 41: 10BASE-T Register (Address 18h, Shadow Value 001).................................................................. 97

Table 42: 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Register

(Address 18h, Shadow Value 010) .................................................................................................99

Table 43: 1000BASE-T/100BASE-TX/10BASE-T Miscellaneous Test Register

(Address 18h, Shadow Value 100) ............................................................................................... 100

Table 44: 1000BASE-T/100BASE-TX/10BASE-T Miscellaneous Control Register

(Address 18h, Shadow Value 111) ............................................................................................... 102

Table 45: 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Summary Register (Address 19h) ......... 104

Table 46: 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (Address 1Ah).......................... 106

Table 47: 1000BASE-T/100BASE-TX/10BASE-T Interrupt Mask Register (Address 1Bh) ........................... 110

Table 48: 1000BASE-T/100BASE-TX/10BASE-T Register 1Ch Shadow Values.......................................... 111

Table 49: 1000BASE-T/100BASE-TX/10BASE-T Spare Control 1 Register

(Address 1Ch, Shadow Value 00010) .......................................................................................... 111

Table 50: Default LED1 and LED2 Status ..................................................................................................... 112

Table 51: Linkspeed LED1 and LED2 Status (LOM-LED Mode) ................................................................... 113

Table 52: 1000BASE-T/100BASE-TX/10BASE-T Clock Alignment Control Register

(Address 1Ch, Shadow Value 00011) .......................................................................................... 113

Table 53: 1000BASE-T/100BASE-TX/10BASE-T Spare Control 2 Register

(Address 1Ch, Shadow Value 00100) .......................................................................................... 114

Table 54: 1000BASE-T/100BASE-TX/10BASE-T Spare Control 3 Register

(Address 1Ch, Shadow Value 00101) .......................................................................................... 115

Table 55: 1000BASE-T/100BASE-TX/10BASE-T LED Status Register

(Address 1Ch, Shadow Value 01000) .......................................................................................... 116

Table 56: 1000BASE-T/100BASE-TX/10BASE-T LED Control Register

(Address 1Ch, Shadow Value 01001) .......................................................................................... 118

Table 57: Auto Power-Down Register (Address 1Ch, Shadow Value 01010) ............................................... 119

Table 58: 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Register

(Address 1Ch, Shadow Value 01101) .......................................................................................... 121

Table 59: 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Control/Status Register

(Address 1Ch, Shadow Value 01111) .......................................................................................... 122

Table 60: 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Register

(Address 1Dh) Bit[15] = 1’b0 ........................................................................................................ 123

List of TablesBCM54213PE Data Sheet

BROADCOM CONFIDENTIAL

Broadcom

November 23, 2015 • 54213PE-DS102-R Page 20

Table 61: 1000BASE-T/100BASE-TX/10BASE-T HCD Status Register (Address 1Dh) Bit[15] = 1’b1 ......... 124

Table 62: 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (Address 1Eh) ........................................ 127

Table 63: Expansion Register 00h: Receive/Transmit Packet Counter ......................................................... 128

Table 64: Expansion Register 04h: Multicolor LED Selector ......................................................................... 128

Table 65: Expansion Register 05h: Multicolor LED Flash Rate Controls....................................................... 130

Table 66: Expansion Register 06h: Multicolor LED Programmable Blink Controls........................................ 131

Table 67: Expansion Register 08h: 10BT Controls........................................................................................ 132

Table 68: Expansion Register 70h: Soft Reset .............................................................................................. 132

Table 69: WOL Register 80h: WAKE_ON_LAN_MAIN_CONTROL Register ............................................... 133

Table 70: WOL Register 81h: INNER_TAG_PROTOCAL_ID Register ......................................................... 135

Table 71: WOL Register 82h: OUTER_TAG_PROTOCAL_ID Register........................................................ 136

Table 72: WOL Register 83h: OUTER_TAG_PROTOCAL_ID_2 Register.................................................... 136

Table 73: WOL Register 84h: MAGIC_PACKET1_DATA_BIT[15:0] Register............................................... 136

Table 74: WOL Register 85h: MAGIC_PACKET1_DATA_BIT[31:16] Register............................................. 136

Table 75: WOL Register 86h: MAGIC_PACKET1_DATA_BIT[47:32] Register............................................. 137

Table 76: WOL Register 87h: MAGIC_PACKET2/SECUREKEY_DATA_BIT[15:0] Register ....................... 137

Table 77: WOL Register 88h: MAGIC_PACKET2/SECUREKEY_DATA_BIT[31:16] Register ..................... 138

Table 78: WOL Register 89h: MAGIC_PACKET2/SECUREKEY_DATA_BIT[47:32] Register ..................... 138

Table 79: WOL Register 8Ah: SECUREKEY_DATA_BIT[63:48]

(SECUREKEY_8_BYTE_MODE) Register................................................................................... 139

Table 80: WOL Register 8Bh: WAKE_ON_LAN_PACKET_MASK_CONTROL[15:0] Register .................... 139

Table 81: WOL Register 8Ch: WAKE_ON_LAN_PACKET_MASK_CONTROL[31:16] Register .................. 139

Table 82: WOL Register 8Dh: WAKE_ON_LAN_PACKET_MASK_CONTROL[47:32] Register .................. 140

Table 83: WOL Register 8Eh: WAKE_ON_LAN_SECURE_KEY_DATA_STORAGE[15:0] Register ........... 140

Table 84: WOL Register 8Fh: WAKE_ON_LAN_SECURE_KEY_DATA_STORAGE[31:16] Register ......... 140

Table 85: WOL Register 90h: WAKE_ON_LAN_SECURE_KEY_DATA_STORAGE[47:32] Register.......... 140

Table 86: WOL Register 91h: WAKE_ON_LAN_SECURE_KEY_DATA_STORAGE[63:48] Register.......... 141

Table 87: WOL Register 92h: MAGIC_PACKET_1/2_SHARED_COUNTER Register ................................. 141

Table 88: WOL Register 93h: MAGIC_PACKET_INTERRUPT_MASK Register .......................................... 141

Table 89: WOL Register 94h: MAGIC_PACKET_STATUS_INTERRUPT Register ...................................... 142

Table 90: Top-MISC Register 00h: MII_BUF_CNTL_0 Register ................................................................... 142

Table 91: Configurable_Wait_State_Timer Settings...................................................................................... 143

Table 92: Configurable_Wait_State_Timer Settings...................................................................................... 143

Table 93: Top-MISC Register 06h: IDDQ_CTL Register ...............................................................................144

Table 94: Top-MISC Register 07h: PIN_CTL Register .................................................................................. 144

Table 95: Top-MISC Register 0Ch: LED_CTL Register ................................................................................145

Table 96: EEE Capability Register................................................................................................................. 146

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