MIPIPhysicalLayersM-PHYD-PHYC-PHY.pdf_ifconfig:SIOCSIFFLAGS:Nosuchdevice

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Overview

MIPI Alliance provides a set of specialized physical layers with both complementary and unique features to support a wide variety

of application protocols requiring high performance, low-power serial interfaces. MIPI denes camera, display, and chip-to-chip

protocol Specications that each support M-PHY, D-PHY and/or C-PHY; MIPI also cooperates closely with independent partner

organizations to create widely adopted industry specications that use M-PHY.

Each physical layer oers unique advantages and features that collectively address every important aspect of today’s integrated

handheld mobile devices.

M-PHY (v3.1, June 2014)

M-PHY is an embedded clock serial interface technology with ultra-high

bandwidth capabilities, specically developed for the extreme performance

and low power requirements of mobile applications. It’s designed for next

generation point-to-point interfaces and high speed component networks

using dual simplex architectures. M-PHY currently supports seven dierent

protocols, from advanced cameras to high speed memory, where low pin

count, lane scalability and power eciency are paramount requirements.

By transmitting in long or short bursts, M-PHY adapts to a wide range of

requirements while minimizing power consumption. Additionally, it operates

over various media types, including optical interconnects, by supporting

Media Converters.

D-PHY (v1.2, September 2014)

D-PHY is a serial interface technology using dierential signaling for band-

limited channels with scalable data lanes and a source synchronous clock to

support power ecient interfaces for streaming applications such as displays

and cameras. It oers half-duplex behavior for applications that benet from

bidirectional communication at transmission rates up to 2.5 Gigabit per lane.

C-PHY (v1.0, October 2014)

C-PHY requires few conductors, does not require a separate clock lane,

and provides flexibility to assign individual lanes in any combination

to any port on the application processor via software control. Due

to similarities in basic electrical specifications, C-PHY and D-PHY can

be implemented on the same device pins. 3-phase symbol encoding

technology delivers approximately 2.28 bits per symbol over a three-

wire group of conductors per lane. This enables higher data rates at a

lower toggling frequency, further reducing power.

Target Applications

• Mobile Applications

• Camera

• Display

• Chip-to-chip Interconnect

• Storage

• Memory

Key Features

• Low Power

• Low Pin Count

• Minimize interference

• Optional support for optical interconnects

(M-PHY)

Key Benets

• High Performance

• High Scalability

• High Bandwidth

• Unprecedented Flexibility

Support by the Industry

• Shipping in millions of mobile products

• JEDEC Universal Flash Storage

• Mobile PCIexpress

• USB SSIC

FEATURES

SPECIFICATION BRIEF

Physical Layers: M-PHY®, D-PHY, C-PHY

The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI. All materials contained herein are protected by

copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI®, M-PHY®,

UniPro

, MIPI Alliance and the dotted rainbow arch and all related trademarks, trade names, and other intellectual property are the exclusive property of MIPI Alliance. All other trademarks, service marks, registered

trademarks, and registered service marks are the property of their respective owners.

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