cadence放大器模拟测试参数教程_cadenceSlewRate - CSDN文库

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Design steps taken from

1) www.ece.utah.edu/~harrison/ece5720/opampsim1.pdf

2) www.ece.utah.edu/~harrison/ece5720/opampsim2.pdf

This assignment will take you through the simulation and basic characterization of a simple

operational amplifier (opamp).

While most digital circuits use a single-polarity power supply (e.g., vdd and gnd), many

analog circuits . especially op amps are powered by a dual-polarity power supply (e.g., vdd,

vss, and gnd). By convention, vdd is positive relative to gnd (e.g.,+1.2V) and vss is negative

relative to gnd (e.g., -1.2V). The use of dual-polarity power supplies allows us to center ac

signals at gnd and build circuits capable of generating signals that swing above and below

gnd by a few volts.

However the current technology offers only single polarity supply where the vdd=1.2V and

the negative supply is gnd=0V. In order to design the opamp we need to redefine the single

polarity supply using the analog ground gnda.

This voltage can be given by the component gnda from the analogLib library in cadence

gnda=600m. So now we have something similar to a dual polarity supply in the current

technology to design the opamps.

Dual Polarity Single Polarity

VDD 2.5V vdd 1.2V

Gnd 0V gnda 600mV

VSS -2.5V gnd 0V

As you can see vdd is positive relative to gnda (e.g.,+600mV) and gnd is negative relative to

gnda (e.g., -600mV). We can use the dual-polarity power supplies to center ac signals at gnda

and build circuits capable of generating signals that swing above and below gnda by a few

hundred millivolts.

Important tips: Tie the substrate to gnd. The rule we must always obey is this: Always tie the

substrate to the most negative voltage in the circuit. In our case the gnd is the most negative

voltage of all since it has the lowest voltage of 0V. Remember, when in simulation, always tie

the bodies of all nMOS transistors to the most negative voltage (i.e. gnd), and always tie the

bodies of all pMOS transistors highest voltage (i.e. vdd) if it is a single well process.

Power supply design for your entire DAC

Use the following diagram for the power supply in

cadence simulations. Make sure all your signals are

centered on the gnda.

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评论4

xuelang00z

2013-10-14

内容很实用，谢谢楼主分享

bestmyjj

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