IEEEStd1364-2005-IEEEStandardforVerilogHardwareDescriptionLanguage.pdf_generateblock

IEEE标准

Verilog

需积分: 50 70 浏览量更新于2023-03-03 评论 1 收藏 6.16MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源评论

资源推荐

IEEE Std 1364™-2005

(Revision of IEEE Std 1364-2001)

IEEE Standard for Verilog

Hardware Description Language

I E E E

3 Park Avenue

New York, NY 10016-5997, USA

7 April 2006

IEEE Computer Society

Sponsored by the

Design Automation Standards Committee

Authorized licensed use limited to: Nokia. Downloaded on January 08,2019 at 09:24:27 UTC from IEEE Xplore. Restrictions apply.

IEEE Standards documents are developed within the IEEE Societies and the Standards Coordinating

Committees of the IEEE Standards Association (IEEE-SA) Standards Board. The IEEE develops its standards

through a consensus development process, approved by the American National Standards Institute, which brings

together volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are not

necessarily members of the Institute and serve without compensation. While the IEEE administers the process

and establishes rules to promote fairness in the consensus development process, the IEEE does not independently

evaluate, test, or verify the accuracy of any of the information contained in its standards.

Use of an IEEE Standard is wholly voluntary. The IEEE disclaims liability for any personal injury, property or

other damage, of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly or

indirectly resulting from the publication, use of, or reliance upon this, or any other IEEE Standard document.

The IEEE does not warrant or represent the accuracy or content of the material contained herein, and expressly

disclaims any express or implied warranty, including any implied warranty of merchantability or fitness for a spe-

cific purpose, or that the use of the material contained herein is free from patent infringement. IEEE Standards

documents are supplied “AS IS.”

The existence of an IEEE Standard does not imply that there are no other ways to produce, test, measure,

purchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, the

viewpoint expressed at the time a standard is approved and issued is subject to change brought about through

developments in the state of the art and comments received from users of the standard. Every IEEE Standard is

subjected to review at least every five years for revision or reaffirmation. When a document is more than five

years old and has not been reaffirmed, it is reasonable to conclude that its contents, although still of some value,

do not wholly reflect the present state of the art. Users are cautioned to check to determine that they have the

latest edition of any IEEE Standard.

In publishing and making this document available, the IEEE is not suggesting or rendering professional or other

services for, or on behalf of, any person or entity. Nor is the IEEE undertaking to perform any duty owed by any

other person or entity to another. Any person utilizing this, and any other IEEE Standards document, should rely

upon the advice of a competent professional in determining the exercise of reasonable care in any given

circumstances.

Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate to

specific applications. When the need for interpretations is brought to the attention of IEEE, the Institute will initiate

action to prepare appropriate responses. Since IEEE Standards represent a consensus of concerned interests, it is

important to ensure that any interpretation has also received the concurrence of a balance of interests. For this

reason, IEEE and the members of its societies and Standards Coordinating Committees are not able to provide an

instant response to interpretation requests except in those cases where the matter has previously received formal

consideration. At lectures, symposia, seminars, or educational courses, an individual presenting information on

IEEE standards shall make it clear that his or her views should be considered the personal views of that individual

rather than the formal position, explanation, or interpretation of the IEEE.

Comments for revision of IEEE Standards are welcome from any interested party, regardless of membership affil-

iation with IEEE. Suggestions for changes in documents should be in the form of a proposed change of text,

together with appropriate supporting comments. Comments on standards and requests for interpretations should

be addressed to:

Secretary, IEEE-SA Standards Board

445 Hoes Lane

Piscataway, NJ 08854

USA

Authorization to photocopy portions of any individual standard for internal or personal use is granted by the Insti-

tute of Electrical and Electronics Engineers, Inc., provided that the appropriate fee is paid to Copyright Clearance

Center. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service,

222 Rosewood Drive, Danvers, MA 01923 USA; +1 978 750 8400. Permission to photocopy portions of any indi-

vidual standard for educational classroom use can also be obtained through the Copyright Clearance Center.

NOTE−Attention is called to the possibility that implementation of this standard may require use of subject

matter covered by patent rights. By publication of this standard, no position is taken with respect to the

existence or validity of any patent rights in connection therewith. The IEEE shall not be responsible for

identifying patents for which a license may be required by an IEEE standard or for conducting inquiries into the

legal validity or scope of those patents that are brought to its attention.

Authorized licensed use limited to: Nokia. Downloaded on January 08,2019 at 09:24:27 UTC from IEEE Xplore. Restrictions apply.

Introduction

The Verilog hardware description language (HDL) became an IEEE standard in 1995 as IEEE Std 1364-

1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard

textual format for a variety of design tools, including verification simulation, timing analysis, test analysis,

and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice

by an overwhelming number of integrated circuit (IC) designers.

Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,

and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is

essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in

which expressions of both variables and nets can continuously drive values onto nets, provide the basic

structural construct. Procedural assignments, in which the results of calculations involving variable and net

values can be stored into variables, provide the basic behavioral construct. A design consists of a set of mod-

ules, each of which has an input/output (I/O) interface, and a description of its function, which can be struc-

tural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets.

The Verilog language is extensible via the programming language interface (PLI) and the Verilog proce-

dural interface (VPI) routines. The PLI/VPI is a collection of routines that allows foreign functions to access

information contained in a Verilog HDL description of the design and facilitates dynamic interaction with

simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation

and computer-assisted design (CAD) systems, customized debugging tasks, delay calculators, and

annotators.

The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel Univer-

sity in England under a contract to produce a test generation system for the British Ministry of Defense.

HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification

simulation, timing analysis, fault simulation, and test generation.

In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent

Open Verilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board of

Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993, the first IEEE

working group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard as

IEEE Std 1364-1995.

After the standardization process was complete, the IEEE P1364 Working Group started looking for feed-

back from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. This

led to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001.

With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identify

outstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-

ing on standardizing SystemVerilog in 2001, additional issues were identified that could possibly have led to

incompatibilities between Verilog 1364 and SystemVerilog. The IEEE P1364 Working Group was estab-

lished as a subcomittee of the SystemVerilog P1800 Working Group to help ensure consistent resolution of

such issues. The result of this collaborative work is this standard, IEEE Std 1364-2005.

This introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog

Hardware Description Language.

Authorized licensed use limited to: Nokia. Downloaded on January 08,2019 at 09:24:27 UTC from IEEE Xplore. Restrictions apply.

剩余589页未读，继续阅读

Alonger1988

粉丝: 14
资源: 10

会员权益专享

IEEE Std 1364-2005-IEEE Standard for Verilog Hardware Descriptio...

评论0

会员权益专享

最新资源

IEEE Std 1364-2005-IEEE Standard for Verilog Hardware Descriptio...

评论0

IEEE Standard for Verilog 2005

IEEE Standard for Verilog

IEEE Standard 1364-2001 Verilog Hardware Description Language

verilog标准ieee std 1364 2005.pdf

《ieee.1364-verilog-2005》

ieee 1364-2005标准

verilog_ieee官方标准手册-2005_ieee_p1364

verilog_ieee官方标准手册-2005

verilog学习资料啊

Verilog HDL 的历史

IEEE Verilog

ieee 1800-2017 system verilog pdf

verilog HDL

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL entity display is port( clock: in std_logic; reset: in std_logic; input: in std_logic_vector(3 downto 0); output: out std_logic_vector(7 downto 0) ); end display;检验这个代码的正确性

systemverilog ieee 1800-2017.pdf

by verilog hdl

pcie verilog

AN430 Verilog

Verilog &a[2:0]

Verilog IDLE

会员权益专享

最新资源